Semiconductor device

Details Semiconductor device Semiconductor device

2001-11-20

2003-12-09

Thompson, Craig (Department: 2813)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Bump leads

Reexamination Certificate

active

06661093

ABSTRACT:

BACKGROUND OF THE INVENTION
This invention concerns a semiconductor device and a manufacturing technique thereof and, more specifically, it relates to a technique effective for application to a semiconductor device manufactured by a process of forming Cu (copper) wirings and solder bumps on Al wirings prior to the step of dividing into semiconductor chips a semiconductor wafer in which circuit elements and Al (aluminum) wirings are formed.
A packaging technique called as a wafer level CSP (Chip Scale Package) or a wafer process package (Wafer Process Package: WPP) of integrating a package process (post-step) and a wafer process (pre-step) and forming a solder bump in each chip region of a semiconductor wafer prior to the step of dividing a semiconductor wafer, in which circuit elements and Al wirings are formed, into semiconductor chips is adapted to treat the package process by applying the wafer process and, accordingly, has an advantage capable of drastically reducing the number of steps compared with the existent method of treating the package process (post-step) on every semiconductor chips cut out of a semiconductor wafer. The wafer level CSP is described, for example, in “Nikkei Microdevice”, p 38 to p 63 issued from Nikkei BP Co. (Feb. 1, 1999) or International Laid-Open No. WO99/23696 and corresponding U.S. patent application Ser. Nos. 09/530,490 and 09/627,008.
In the semiconductor device where the external connection terminals of the semiconductor chip is constituted of the solder bump as in the wafer level CSP described above, in a case where circuit elements include memory devices, it is necessary for a countermeasure to avoid soft errors of the memory cell caused by &agr;-rays irradiated from a radio-isotope elements contained, for example, in Pb (lead) in the materials constituting the solder bump.
1999 IEEE Electronic Components and Technology Conference Pb-Free Solder Alloys for Flip Chip Applications discloses a technique of constituting a solder bump using so-called Pb free solder not substantially containing Pb and disposing the solder bumps in a peripheral circuit region other than the memory cell forming region.
Japanese Published Unexamined Patent Application Hei 11(1999)-111885 concerns a BGA (Ball Grid Array) in which a wiring pattern for rearrangement is formed of a BLM film (underlayer film pattern formed with an aim of improvement for the adhesion and prevention for inter-diffusion between the electrode pad and the solder bump), which enables &agr;-ray shielding with no provision of additional materials to the existent process, by constituting the BLM film with a metal film (for example, Cu film) with an &agr;-ray shielding ratio of 0.1 or less.
SUMMARY OF THE INVENTION
The present inventors have already developed a wafer process package for forming Cu wirings and solder bumps on Al wirings prior to the step of dividing a semiconductor wafer, in which circuit elements and Al wirings are formed, into semiconductor chips. Since the wafer process package contains memory devices in a portion of the circuit elements, it has been studied to constitute the solder bump with Pb-free solder not substantially containing Pb as a countermeasure for soft error caused by &agr;-rays.
However, when the present inventors have measured &agr;-dose from the Pb-free solder material comprising 98.5% of Sn (tin), 1% of Ag (silver) and 0.5% of Cu, it has been found that &agr;-rays are radiated although a little also from the Pb-free solder material as shown in FIG.
26
. In this case, the measuring time for the &agr;-rays was 200,000 sec and the diameter of the solder bump was 2.5 cm.
While the &agr;-dose contained in the Pb-free solder material is quite a little compared with the &agr;-dose contained in Pb, even the slight amount of &agr;-dose as described above gives innegligible effect on the memory cells in a case where the minimum publication size is reduced to about 0.2 &mgr;m or less.
As a countermeasure for avoiding the effect of &agr;-rays contained in the solder bump, it may be considered to use a solder material at high purity in which the amount of the radioisotope elements is decreased greatly but since the soldering material at high purity is extremely expensive, it is difficult to apply the same to a general purpose wafer process package.
Further, as other &agr;-ray countermeasure, it may be considered a method of not disposing the solder bump above the memory device, increasing to make the thickness of an insulative film interposed between a solder bump connection portion constituted of a portion of Cu wirings (hereinafter also referred to as a bump land) and Al wirings (for example 30 &mgr;m or more) or disposing a thick resin layer additionally between the bump land and the insulative film, thereby shielding &agr;-rays by the insulative film or the resin layer.
However, the method of not disposing the solder bump above the memory device restricts the area for disposing the bump on the semiconductor chip to inevitably narrow the pitch for the solder bumps. Accordingly, since an expensive wiring substrate corresponding to the narrowed pitch has to be provided for mounting the semiconductor chip, it is difficult to apply the method to the general purpose wafer process package. Further, in a case where the thickness of the insulative layer (or resin layer) interposed between the bump land (Cu wirings) and the Al wirings is increased, since the depth of the aperture connecting the Cu wirings formed in the resin insulative layer (or resin layer) and the Al wirings is increased, a large step is formed between the Cu wirings and the Al wirings to bring about another problem of lowering the connection reliability between both of them.
This invention intends to provide a technique capable of preventing &agr;-ray induced soft errors of a semiconductor device manufactured by a process of forming Cu wirings and semiconductor bumps on Al wirings prior to the step of dividing a semiconductor wafer, in which circuit elements and Al wirings are formed, into semiconductor chips.
The foregoings and other objects, as well as novel features of the present invention will become apparent by reading the descriptions of the specification and the appended drawings.
Among the inventions disclosed in the present application, outlines of typical inventions will be explained simply as below.
This invention provides a semiconductor device manufactured by a process of forming Cu wirings and solder bumps on Al wirings prior to the step of dividing a semiconductor wafer, in which circuit elements and Al wirings are formed, into semiconductor chips, wherein the film thickness of the bump electrode connection portion (bump land) is made larger than the film thickness of the bonding pad constituted of a portion of an uppermost Al wiring layer.
According to the device described above, since the &agr;-rays radiated from the radioisotope element in the soldering bump are shielded by the bump electrode connection portion, &agr;-ray induced soft errors can be prevented with no addition of new manufacturing steps or without using expensive materials.


REFERENCES:
patent: 6022792 (2000-02-01), Ishii et al.
patent: 6111317 (2000-08-01), Okada et al.
patent: 11-111885 (1997-10-01), None
patent: WO99/23696 (1997-10-01), None
Albert W. Lin, “Taiwan APack Technologies: Targeting the Hybrid Analog-Digital Chip”, Feb. 1999 Nikkei Microdevice, pp. 1-3; 57.

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