Active solid-state devices (e.g. – transistors – solid-state diode – Gate arrays
Reexamination Certificate
2002-11-22
2003-11-25
Abraham, Fetsum (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Gate arrays
C257S691000, C257S692000
Reexamination Certificate
active
06653671
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device such as a semiconductor memory device and, in particular, to a semiconductor device in which the arrangement of dummy sheets formed on a substrate is improved to planarize the surface of the substrate by a CMP (chemical mechanical polishing).
2. Description of the Related Art
In recent years, in response to the need for a higher-density semiconductor integrated circuit, progress has been made in increasing the number of layers of a multilayer semiconductor device. This increasing the number of layers of a multilayer semiconductor device tends to accumulate and increase roughness (bumps and dips) on the surface of the semiconductor substrate. Such bumps and dips on the surface of the substrate make it difficult to obtain correct focus in an exposure process and thus become one factor in causing defects in a fine pattern lithography. One of technologies solving this problem is the chemical mechanical polishing (hereinafter referred to as “CMP”) which becomes indispensable to a most advanced semiconductor manufacturing process.
However, planarizing the substrate by the CMP is substantially affected by the difference in the arrangement density of metal conductive layers such as a wiring and the like formed on the underlying layer of an insulating layer to be polished. In other words, load applied to the respective metal conductive layers when the substrate is planarized by the CMP becomes larger in the region of the underlying layer where the arrangement density of the metal conductive layers is low than in the region where the arrangement density is high. For this reason, in the insulating layer corresponding to the underlying layer where the arrangement density of the metal conductive layers is low, a polishing rate becomes larger. This causes bumps and dips on the surface of the semiconductor substrate even after the CMP is applied to the surface.
Such existence of bumps and dips affect the manufacturing conditions of the following processes. For example, in the case where through holes are made in the substrate after the substrate is subjected to the CMP, the through holes are made in different depths in accordance with the bumps and dips. This causes metal in the through hole to enter a portion not intended, for example, to cause a defect of producing a leak current. Therefore, it is necessary to put a dummy pattern previously at a mask designing step for a region where the arrangement density of the metal conductive layer on the semiconductor substrate is low.
FIG. 5
is a plan view to show an example of the arrangement of dummy sheets provided when the memory array part of a semiconductor memory device is formed. In
FIG. 5
, a reference numeral
100
denotes a semiconductor substrate constituting a memory array part in which memory cells and a plurality of word lines and a plurality of bit lines of their signal lines are formed in a matrix. A reference numeral
101
denotes a dummy sheet and the dummy sheets
101
are arranged in an array irrespective of the arrangement layout of the memory cells on the substrate
100
that is an underlying layer. Moreover, for the memory array part of the semiconductor memory device, in general, rectangular dummy sheets
101
are used as the simplest dummy pattern.
As shown in
FIG. 5
, arranging the dummy sheets
101
in an array on the substrate
100
can relax the effect produced by the difference in the arrangement density of the memory cells, the word lines, and the bit lines formed on the underlying layer, and thus can reduce the dumps and dips formed on the surface of the substrate after the substrate is subjected to the CMP. Moreover, as the semiconductor manufacturing process progresses, the case has increased in number where the dummy sheet becomes larger in size than the memory cell. For this reason, there is also the case where the plurality of dummy sheets
101
are arranged close to each other such that each of them spreads over two neighboring word lines.
Since the semiconductor device in the prior art is constituted in the manner described above, it presents a problem that the capacitive coupling of the dummy sheets provided for the CMP and the wirings of the underlying layer might cause a defect in the operation.
For example, when it is supposed that a case where a plurality of dummy sheets
101
are arranged in the direction of row in such a way that each of them spreads over two neighboring word lines in the semiconductor memory device shown in FIG.
5
. In this example of arrangement, a plurality of blocks each of which includes a group of dummy sheets
101
arranged in such a way that each of them spreads over two neighboring word lines are arranged along the direction of column. When an electric signal is propagated in the word line in the semiconductor memory device having such a configuration, in the respective blocks described above, the dummy sheets
101
are capacitively coupled to the word lines in various degrees.
For example, in the case where the dummy sheet is large in size and two neighboring blocks are different from each other in coupling capacity, an electric interference might be produced between the word lines via the dummy sheet
101
. The electric interference caused by variations in coupling capacity between the dummy sheet
101
and the word line may produce a serious effect on the operation of the semiconductor memory device.
Further, analyzing the defects of the semiconductor device becomes an effective countermeasure for an improvement of yield that is always a problem in manufacturing the semiconductor device. In particular, a physical arrangement information of the constituent part that is found to be defective becomes an important parameter in the analysis of the defect. In the semiconductor device in the prior art, however, the dummy sheets for the CMP are arranged uniformly without reference to the layout of the constituent parts of the underlying layer.
For this reason, it is difficult to discriminate from outward appearances which constituent part is arranged in the underlying layer of the dummy sheets, which presents the problem that it is difficult to obtain the physical arrangement information of the constituent part which is found to be defective.
SUMMARY OF THE INVENTION
The present invention has been made to solve the problems described above. It is an object of the present invention to provide a semiconductor device capable of reducing the electric interference between wirings on an underlying layer via dummy sheets arranged for the CMP.
Moreover, it is another object of the present invention to provide a semiconductor device capable of easily obtaining the physical arrangement information of constituent parts provided on the underlying layer of dummy sheets.
A semiconductor device in accordance with the present invention includes a wiring layer which is formed on a semiconductor substrate and in which a plurality of wirings are arranged in parallel, and a dummy pattern including a plurality of blocks each of which has a plurality of dummy sheets arranged in such a way that each of them spreads over two wirings neighboring in the direction along the wiring and a plurality of dummy sheets arranged between the plurality of blocks in such a way that each of them spreads over two wirings neighboring between the blocks.
Moreover, a semiconductor device in accordance with the present invention includes a wiring layer which is formed on a semiconductor substrate and in which a plurality of wirings are arranged in parallel, the first layer in which a plurality of dummy sheets are arranged on the wirings in the direction along the wiring, the second layer in which the dummy sheets are arranged in such a way that each of them spreads over two neighboring dummy sheets arranged on the first layer, and an electric connection parts for electrically connecting the dummy sheets arranged on the first layer to the dummy sheets arranged on the second layer, respectively.
Therefore, accordin
Okamoto Kazuyoshi
Wakasugi Hirohiko
Abraham Fetsum
Burns Doane , Swecker, Mathis LLP
Mitsubishi Denki Kabushki Kaisha
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