Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum
Reexamination Certificate
2001-04-10
2003-02-04
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified material other than unalloyed aluminum
C257S781000, C257S786000, C257S784000, C438S622000
Reexamination Certificate
active
06515364
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to a semiconductor device and more particularly to a semiconductor device having a pad for use in creating electrical connections with external devices.
BACKGROUND OF THE INVENTION
In order to reduce the chip size of semiconductor devices, minimum device geometries have decreased. As geometries on semiconductor devices have decreased, minimum geometries for metal wirings have been reduced to the submicrometer range. However, a bond wire, used for electrical connection between a semiconductor device and a conducting portion of a lead frame, can have a diameter of 20 to 50 &mgr;m. A pad electrode (bond pad) provides a conducting contact surface on the semiconductor device for a bond wire. The pad electrode can form a square conducting layer with each side being about 100 &mgr;m in order to provide adequate surface area for the bonding wire contact surface.
In conventional semiconductor devices, the pad electrode can become thinner following the reduced geometries for conductors. However, a thinner pad electrode can be more likely to peel from the semiconductor surface due to impact forces.
For example, in a semiconductor device such as an Static Random Access Memory (SRAM), Dynamic Random Access Memory (DRAM), or Mask Read Only Memory (Mask ROM), an aluminum wiring having a 0.4 &mgr;m width can be formed on the semiconductor substrate in order to provide a low resistance conductor to gate electrodes in the memory cells along a word line. It may be desirable to form this aluminum wiring in the same process step as the pad electrode in order to keep the number of process steps low and thus keep manufacturing costs low. However, in order to accurately etch an aluminum wiring having a 0.4 &mgr;m width and a 0.4 &mgr;m spaced interval, it is desirable that the thickness of the deposited aluminum film to be less than 0.4 &mgr;m.
In contrast, in order to prevent the pad electrode from being susceptible to peeling from the semiconductor surface due to impact forces during the bonding process, the thickness of the aluminum film is desired to be at least 0.6 &mgr;m. This can make it difficult to reduce the size of the semiconductor device.
A semiconductor device was disclosed in Japanese Patent No. 2964999 ('999) constructed in a manner to improve the adhesion force between a pad electrode and an interlayer insulation film. The semiconductor device in the '999 includes a conductive film formed on a semiconductor substrate, an interlayer film formed on the conductive film, the interlayer film having an opening in which a metal layer is formed. A pad electrode is then formed on the interlayer film.
In the '999, the metal layer formed in the opening of the interlayer film has a height that is slightly lower than the top of the opening. This forms irregularities or unevenness on the interface between the pad electrode and the interlayer film. This can help prevent slippage from occurring at the interface between the pad electrode and the interlayer film. Thus, adhesion may be improved and peeling of the pad electrode can be reduced when the bond wire is bonded to the pad electrode.
In the semiconductor device disclosed in the '1999, a Local Oxidation of Silicon (LOCOS) isolation method of up to 0.24 &mgr;m is used to create the interface layer, which is used as a base for the pad electrode. This ensures a flat enough interface layer, which is used as a device isolation area. The conductive film and metal layer can also serve as an anchor for the pad electrode.
In recent semiconductor devices, a Shallow Trench Isolation (STI) method can be used in order to have more control over device isolation areas.
An example of a conventional semiconductor device having a pad electrode that uses STI method to form the device isolation area will now be illustrated with reference to
FIGS. 1A and 1B
.
FIG. 1A
sets forth a plan view of a pad electrode of a conventional semiconductor device.
FIG. 1B
sets forth cross-sectional view of the pad electrode of
FIG. 1A
as viewed through the line A—A.
Referring now to
FIGS. 1A and 1B
, in the conventional semiconductor device a buried oxide film
51
having a thickness of 0.2 to 0.4 &mgr;m is formed on a p-type silicon substrate
50
. Buried oxide
51
is formed in the pad electrode formation area using a STI method. Polycide
52
is formed on the buried oxide film
51
. From
FIG. 1A
, it can be seen that polycide
52
is formed in a matrix with each square having sides of 4 &mgr;m length.
Interlayer film
53
is then formed on buried oxide film
53
and polycide film
52
. A plurality of contact holes
54
having dimensions of 0.3 &mgr;m by 0.3 &mgr;m are formed in interlayer film
53
. Each square polycide region
52
has twenty-five contact holes
54
arranged in five rows and five columns as can be seen in FIG.
1
A. There are 14,400 contact holes
54
formed under the 100 &mgr;m square pad electrode
57
.
Barrier film
55
comprising a layered Ti/TiN is formed on interlayer film
53
and within contact holes
54
. A plug
56
comprising buried tungsten is then formed on the barrier film
55
in the contact holes
54
. A pad electrode
57
comprising an AlCu film is formed on then formed on interlayer film
53
containing barrier film
55
and plug
56
. Pad electrode
57
is a square having 100 &mgr;m sides and has a thickness of 0.5 to 0.6 &mgr;m.
As mentioned previously, in the conventional semiconductor device illustrated in
FIGS. 1A and 1B
, the buried oxide
51
is formed using a STI method. In the STI method, a trench having a depth of 0.2 to 0.4 &mgr;m is formed in p-type silicon substrate
50
. An oxide film is then formed on the p-type silicon substrate
50
using a High Density Plasma (HDP) Chemical Vapor Deposition (CVD) method. The oxide film is then polished with a Chemical Mechanical Polis (CMP) to form buried oxide film
51
in the trench.
The CMP is performed over an about 100 &mgr;m wide square region. When CMP is performed over such a large area, uneven pressure distributions can cause “dishing” to occur by varying removal rates of selected material within the region during the CMP. “Dishing” can deteriorate the flatness of buried oxide film
51
. If the pad electrode
57
is formed when “dishing” has occurred, there may be a 0.1 &mgr;m difference in the height between the center and an edge of the pad electrode
57
.
If the surface of buried oxide film
51
, which serves as a foundation for the pad formation, is uneven; the flatness of polycide
52
formed on buried oxide film
51
can also deteriorate. This can result in a further uneven configuration of contact holes
54
formed on polycide
52
.
The bonding force between pad electrode
57
and interlayer film
53
can be reduced. This can result in stripping or peeling of the pad electrode
57
.
If the thickness of pad electrode
57
is increased, stripping or peeling may be prevented. However, as discussed earlier, increasing the thickness of pad electrode
57
can reduce the etching accuracy of a wiring layer formed in the same process step as the pad electrode
57
. Thus, minimum wiring geometries can be adversely affected.
Also, the conventional semiconductor device as illustrated in
FIGS. 1A and 1B
has a drawback in that when-the thickness of buried oxide film
51
is uneven, there may be thinner regions in which the breakdown voltage between pad electrode
57
and p-type silicon substrate
50
is reduced. This can cause electrostatic discharge (ESD) properties to deteriorate.
In view of the above discussion, it would be desirable to provide a semiconductor device in which a pad electrode can be resistant to peeling or stripping as compared to conventional approaches. Still further it would also be desirable to have improved ESD properties. It would also be desirable to have finer device fabrication capabilities.
SUMMARY OF THE INVENTION
According to the present embodiments, a semiconductor device having a pad formation region can include device isolation regions and impurity regions formed in an alt
Huynh Andy
NEC Corporation
Nelms David
Sako Bradley T.
Walker Darryl G.
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