Semiconductor device

Details Semiconductor device Semiconductor device

2001-07-30

2003-12-30

Loke, Steven (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Physical configuration of semiconductor

With specified crystal plane or axis

C257S628000, C257S411000, C257S496000

Reexamination Certificate

active

06670694

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2001-165581, filed May 31, 2001, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a semiconductor device and more particularly to a CMOS (Complementary Metal Oxide Semiconductor) device used in an LSI (Large Scale Integrated Circuit) of high performance and low power consumption, for example.
2. Description of the Related Art
For attaining the high performance of a CMOS device, the technique for forming a non-doped epitaxial silicon layer in the channel portion to form a field effect transistor (MOSFET) is already known (for example, K. Noda, T. Uchida, T. Tatsumi, T. Aoyama, K. Nakajima, H. Miyamoto, T. Hashimoto and I. Sasaki, “0.1 &mgr;m delta doped MOSFET using post low-energy implanting selective epitaxy,” in Symp. VLSI Tech. Dig., pp. 19-20, 1994. (refer to reference document [1]), or T. Ohguro, H. Naruse, H. Sugaya, S. Nakamura, N. Sugiyama, E. Morifuji, H. Kimijima, T. Yoshitomi, T. Morimoto, H. S. Momose, Y. Katsumata and H. Iwai, “Silicon epitaxy and its application to RF IC's”, Electrochemical society proceeding vol. 99-18, pp. 123-141, 1999. (refer to reference document [2])).
It is known that the transistor with the above structure enhances the driving power and has an excellent sub-threshold characteristic and is effective for lowering a gate leakage current which causes a problem in a fine MOSFET (for example, H. S. Momose, T. Ohguro, E. Morifuji, H. Sugaya, S. Nakamura, T. Yoshitomi, H. Kimijima, T. Morimoto, F. Matsuoka, Y. Katsumata, H. Ishiuchi and H. Iwai, “Improvement of direct-tunneling gate leakage current in ultra-thin gate oxide CMOS with TiN gate electrode using non-doped selective epitaxial Si channel technique”, in IEDM Tech. Dig. pp 819-822, December, 1999. (refer to reference document [3]).
FIG.
22
A and
FIG. 22B
show a method for manufacturing a transistor with the above structure by taking a conventional CMOS device as an example.
First, as shown in
FIG. 22A
, an element isolation region
102
is formed in the surface portion of a silicon substrate
101
having a normal (100) surface orientation so as to define element regions (N-type well region
103
a,
P-type well region
103
b
). After a silicon sacrificing oxide film (not shown) with a film thickness of 12 nm is formed on the surfaces of the N-type well region
103
a
and P-type well region
103
b,
arsenic and boron which are impurities are doped. Thus, a PMOS channel impurity doped region
104
a
and NMOS channel impurity doped region
104
b
are formed as channel portions each having a desired threshold voltage.
Then, after the silicon sacrificing oxide film is removed, a pre-heating process at 940° C. is effected as a pre-process for removing residual oxygen in the surface portion of the silicon substrate
101
.
Next, silicon epitaxial growth layers (non-doped epitaxial silicon layers)
105
a,
105
b
are respectively formed with a film thickness of approx. 30 nm on the PMOS channel impurity doped region
104
a
and NMOS channel impurity doped region
104
b
by use of Si
2
H
4
Cl
2
gas, for example, at the temperature of 800° C. by the reduced pressure chemical vapor deposition (RP-CVD) method. By effecting the above process, a channel portion having an extremely steep impurity concentration gradient is realized.
After this, as shown in
FIG. 22B
, the gate oxidation process is effected by a furnace oxidation method. By effecting the above gate oxidation process, oxide films used for respectively forming gate insulating films
106
a,
106
b
with the preset film thickness are formed on the silicon epitaxial growth layers
105
a,
105
b.
For example, if the gate oxidation process is effected in a condition of the temperature of 800° C. and the oxidizing time of 60 minutes, an oxide film with a film thickness of 5 nm can be formed. If the furnace oxidation method is used, the gate insulating films
106
a,
106
b
with desired film thickness can be formed by adequately selecting the temperature and time.
Then, after a polysilicon film is deposited on the oxide film to a film thickness of approx. 250 nm, the polysilicon film and oxide film are patterned by anisotropic etching. Thus, gate electrodes
107
a,
107
b
having desired gate length are respectively formed together with the gate oxide films
106
a,
106
b.
Next, after preset impurity is doped, the heat treatment is effected in a nitrogen atmosphere at the temperature of 1000° C. for 20 seconds, for example. By effecting the heat treatment, the impurities in the gate electrodes
107
a,
107
b
are activated and shallow source/drain regions
108
a,
108
b
are formed on the surface portion of the PMOS channel impurity doped region
104
a
and NMOS channel impurity doped region
104
b.
After this, gate side wall portions
109
a,
109
b
and deep source/drain regions
110
a,
110
b
are formed. Thus, a PMOS transistor (P-type MOSFET) and NMOS transistor (N-type MOSFET) respectively having the silicon epitaxial growth layers
105
a,
105
b
in the channel portions thereof are completed.
Then, silicide layers (not shown) are formed on the surface portions of the source/drain regions
110
a,
110
b
and the gate electrodes
107
a,
107
b
by the known technique. After thus lowering the resistance of each of the electrode portions, the electrode portions are connected to metal interconnections (not shown) via contact portions (not shown).
If the N-type MOSFET is formed on the substrate of the (100) surface orientation or if the P-type MOSFET is formed on the substrate of a surface orientation such as the (110) surface orientation other than the (100) surface orientation, it is known that excellent mobility can be attained.
From the above viewpoint, attempt was made to form a MOSFET having a silicon epitaxial growth layer in the channel portion on the substrate of a surface orientation other than the (100) surface orientation. As a result, as described before, it was proved that the reliability of the MOSFET having the silicon epitaxial growth layer in the channel portion was lower than the MOSFET formed on the substrate of the (100) surface orientation and the gate leakage current was increased in comparison with that of the latter MOSFET although it had a preferable structure for enhancing the driving power and attaining the excellent sub-threshold characteristic.
Further, a MOSFET having a channel/gate insulating film interface on the substrate of the (111) surface orientation has a problem that the interface state in the interface between the gate insulating film and the silicon substrate is high and a large number of fixed charges are present in the gate insulating film. That is, the reliability of the transistor is lower than that of a MOSFET having a channel/gate insulating film interface on the substrate of the (100) surface orientation. In practice, in the case of a MOSFET having a gate insulating film of 5 nm thickness, the interface state density of the MOSFET on the substrate of the (111) surface orientation was increased to 2.2 times that of the MOSFET on the substrate of the (100) surface orientation. Further, a variation in the threshold voltage and variations in the transconductance and current driving ability are approximately twice larger.
BRIEF SUMMARY OF THE INVENTION
A semiconductor device according to an embodiment of this invention including field effect transistors each of which has a gate electrode formed on a semiconductor substrate with a gate insulating film disposed therebetween, a semiconductor layer opposite to the gate electrode forming a channel forming region, and source and drain regions formed on both sides of the channel forming region, comprises a first field effect transistor which has an epitaxial growth layer in the channel forming region and in which a surface portion of the channel forming region formed in con

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