Active solid-state devices (e.g. – transistors – solid-state diode – Thin active physical layer which is – Heterojunction
Reexamination Certificate
2002-05-10
2003-12-23
Fahmy, Wael (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Thin active physical layer which is
Heterojunction
C257S577000
Reexamination Certificate
active
06667491
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device including a bipolar transistor, and a method of fabricating such a semiconductor device.
2. Description of the Background Art
A conventional method of fabrication corresponding to formation of a vertical NPN bipolar transistor will be described with reference to
FIGS. 16-26
. Impurities are implanted from the main surface of a silicon substrate
1
to form a P type layer
52
. Then, a P type embedded layer
3
is formed. N type impurities are implanted into P type layer
52
. By annealing, an N type embedded layer
2
is formed. As a result, N type embedded layer
2
is completely surrounded by the P type region in silicon substrate
1
, as shown in FIG.
16
.
Referring to
FIG. 17
, an epitaxial grown layer
4
of a low resistance such as approximately 0.1 &OHgr;·cm is formed having phosphorus doped all over the main surface of silicon substrate
1
. N type embedded layer
2
and P type embedded layer
3
are respectively diffused towards epitaxial grown layer
4
, as shown in
FIG. 17. A
graph of the impurity concentration distribution at the cross section traversing N type embedded layer
2
, i.e. the cross section taken along XVIII—XVIII in
FIG. 17
, is shown in
FIG. 18. A
region corresponding to epitaxial grown layer
4
and silicon substrate
1
are marked along the vertical axes indicating the depth from the surface. A distribution curve
81
indicates the concentration of phosphorus doped into epitaxial grown layer
4
, i.e. the concentration of N type impurities. A distribution curve
82
indicates the concentration of the N type impurities implanted into N type embedded layer
2
. Since epitaxial grown layer
4
is initially formed having phosphorus doped, the concentration of the impurity is constant irrespective of the depth, as appreciated from distribution curve
81
of FIG.
18
. The reason why distribution curve
81
slightly protrudes into silicon substrate
1
is due to the fact that a portion of the impurities formerly included in epitaxial grown layer
4
diffuses into the under-contacting silicon substrate
1
. The N type impurities implanted initially into N type embedded layer
2
diffuse into epitaxial grown layer
4
. Thus, distribution curve
82
of
FIG. 18
exhibits intrusion towards epitaxial grown layer
4
.
A graph of the impurity concentration at a region where there is no impurity layer in
FIG. 17
, i.e. the cross section along XIX—XIX is shown in FIG.
19
. In
FIG. 19
, only a distribution curve
81
is present since there are only N type impurities, i.e. phosphorous, doped into epitaxial grown layer
4
.
Referring to
FIG. 20
, impurities are implanted to predetermined regions in epitaxial grown layer
4
to form a P type isolation diffusion layer
6
and an N type collector leading layer
7
. Then, a field oxide film
5
is formed by LOCOS (local oxidation of silicon). Then, an oxide film
8
is formed at the collector contact region, as shown in FIG.
20
.
Referring to
FIG. 21
, a polysilicon layer is formed all over the surface, followed by ion-implantation of boron of high concentration. Unrequired portions are removed from the polysilicon layer, resulting in an external base
9
by the remaining polysilicon layer. An interlayer oxide film
10
is formed so as to cover the entire surface including external base
9
. Etching is effected to form an opening through interlayer oxide film
10
and external base
9
of polysilicon so as to expose epitaxial grown layer
4
. This opened portion corresponds to an emitter opening
27
. Emitter opening
27
is filled with boron to form an intrinsic base
11
, as shown in FIG.
21
.
Referring to
FIG. 22
, an oxide film spacer
12
is formed to electrically insulate and block external base
9
. Boron is diffused from external base
9
into epitaxial grown layer
4
by thermal treatment, whereby a P type diffusion layer
13
shown in
FIG. 22
is formed.
Referring to
FIG. 23
, a polysilicon layer is formed so as to cover emitter opening
27
. Arsenic is implanted into the polysilicon layer, followed by annealing, whereby arsenic is diffused into intrinsic base
11
to form an N type diffusion layer
14
. The unrequired portion of the polysilicon layer is removed. By the remaining portion of the polysilicon layer, an emitter electrode
15
shown in
FIG. 23
is formed. Oxide film spacers
16
A and
16
B are formed so as to cover respective sidewalls of emitter electrode
15
and external base
9
, respectively. By forming a CoSi film
17
so as to cover the top surface of external base
9
and N type collector leading layer
7
, the parasitic resistance of emitter electrode
15
and external base
9
is reduced.
Referring to
FIG. 24
, an interlayer insulating film
20
is formed. A contact hole is formed in interlayer insulating film
20
. A contact plug
21
is formed by filling the contact hole with a conductor. By connecting the top faces of contact plug
21
with each other through an aluminium line
22
, a vertical NPN bipolar transistor of
FIG. 24
is provided.
A cross sectional view of a further larger range is shown in FIG.
25
. Here, the so-called passive element such as the inductor and capacitor are included here. A polysilicon resistor
18
is included as shown in the cross sectional view of FIG.
25
. Polysilicon resistor
18
is adjusted to a desired resistance by controlling the dopant concentration before interlayer insulating film
20
is formed. Polysilicon resistor
18
is also classified as a passive element. An interlayer insulating film
23
is formed above aluminium line
22
. In the region where a MIM (Metal Insulator Metal) capacitor
31
is formed, an opening is formed deep into interlayer insulating film
23
so that the top face of aluminium line
22
is exposed. A capacitor dielectric film
24
is formed so as to cover the inner face of that opening and the top plane of interlayer insulating film
23
. As shown in
FIG. 26
, an aluminium line
25
is arranged at the top face of capacitor dielectric film
24
above interlayer insulating film
23
. A vertical hole is formed in advance at a predetermined position in interlayer insulating film
23
, arriving at aluminium line
22
. When aluminium line
25
is formed, these vertical holes are filled with a conductor to establish electrical connection between aluminium line
22
and aluminium line
25
. By working on aluminium line
25
, the upper electrode of MIM capacitor
31
, a spiral inductor
32
and a pad
33
are formed. Then, a nitride film
26
that becomes a protection film is grown thereon. An opening is formed in pad
33
. Although not shown, a metal film is formed at the backside of silicon substrate
1
.
Although a method of fabricating a vertical NPN bipolar transistor is shown as conventional art, horizontal PNP bipolar transistors and CMOS transistors are often formed on the same chip in addition to the vertical NPN bipolar transistor generally. Furthermore, although only a polysilicon resistor, a MIM capacitor and a spiral inductor are enumerated as passive elements here, other elements such as a MOS capacitor and a Shottky diode are also formed on the same substrate.
Here, a bipolar transistor including only a junction in silicon has been described as a vertical NPN bipolar transistor. Additionally, a hetero junction bipolar transistor employing SiGe for the base (Silicon Germanium-Hetero Bipolar Transistor: SiGe-HBT) shown in
FIG. 27
is also known. This type of bipolar transistor has a silicon layer
61
, a SiGe layer
62
, and a silicon layer
63
layered respectively by epitaxial growth in order on epitaxial grown layer
4
. Silicon layer
61
includes phosphorus, and functions as a collector layer. SiGe layer
62
includes boron, and functions as a base layer. Silicon layer
63
includes boron. An external base
64
extends from either side thereof. External base
64
corresponds to the junction between the intrinsic base layer and the base electrode, functioning as a bipolar transis
Fahmy Wael
Leydig , Voit & Mayer, Ltd.
Trinh (Vikki) Hoa B.
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