Semiconductor device

Details Semiconductor device Semiconductor device

2000-04-05

2003-06-03

Cuneo, Kamand (Department: 2829)

Electricity: measuring and testing

Measuring, testing, or sensing electricity, per se

With rotor

C714S726000

Reexamination Certificate

active

06573703

ABSTRACT:

BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a semiconductor device in which a circuit to be burned-in is stressed with the use of a scan chain.
(2) Description of the Prior Art
FIG. 1
shows a block diagram of a prior-art semiconductor device. In
FIG. 1
, the reference numeral
1
denotes an entire system of the semiconductor device. The reference numeral
31
denotes a first input terminal. The reference numeral
311
denotes an input signal (input signal line) from the first input terminal. (Hereinafter, “signal lines” are also referred to as “signal”.) The reference numeral
32
denotes a second input terminal. The reference numeral
321
denotes an input signal from the second input terminal. The reference numeral
41
denotes a first output terminal for normal testing, which excludes burn-in testing for eliminating initial failures, and the reference numeral
42
a second output terminal for the normal testing. The reference numeral
2
denotes a subject circuit to be burned-in. The reference numeral
201
denotes a first output signal from the subject circuit
2
, and the reference numeral
202
denotes a second output signal from the subject circuit
2
.
Now, a scan chain in the semiconductor device
1
is explained. A scan chain refers to a circuit (chain) in which plural flip-flops are connected so that an output of a flip-flop is connected to an input of another flip-flop and such connection is repeated to form a chain. The subject circuit
2
in
FIG. 1
includes two scan chains
21
and
22
each configured in such a manner, and corresponding combinational circuits.
In
FIG. 1
, each of the squares
80
denotes a flip-flop, and the circuit
2
is tested with the use of the scan chain
21
provided between the first input terminal
31
and the first output terminal
41
and of the scan chain
22
provided between the second input terminal
32
and the second output terminal
42
.
Next, scan testing using the scan chains is detailed. In scan testing (hereinafter referred to as “scan shift”), since the flip-flops are connected in cascade from the scan input terminal to the scan output terminal, a data can be set at a certain flip-flop by feeding a signal from the scan input terminal. When data are set in the flip-flops, normal operation is performed to operate the combinational circuits and scan shift is again performed to compare signals from the scan output terminal. Testing of the circuits is thus implemented.
When burn-in testing is performed, it is made possible, by repeating a scan shift and a normal operation with the use of scan chains, to operate a subject circuit to a greater degree and thereby to stress the subject circuit with a greater stress. Thus, when implementing burn-in testing using such scan chains, test signals are input from both the first input terminal
31
and the second input terminal
32
in order to stress the subject circuit
2
.
The above-described prior-art semiconductor device, however, has a following drawback. In the prior-art semiconductor device, when the number of scan chains is increased, the number of input terminals is correspondingly increased. However, wafer level burn-in has a limitation in the number of probes. That is, in wafer level burn-in, all the LSIs on a single wafer must be subjected to burn-in, but the number of probes that can be provided for a single wafer is limited. Therefore, as the chip size is reduced, the number of probes that can be provided for each of the LSIs is also reduced. For this reason, if the number of scan chains is excessively increased, wafer level burn-in becomes difficult to implement, and in worst cases, it becomes impossible.
Nevertheless, with recent advances in technology and demands from users which have become increasingly diversified and complicated, chip size of LSIs has been made further smaller.
Accordingly, there is a need for a simple and low-cost semiconductor device that does not require a large number of input terminals necessary for burn-in testing.
In addition, with increasingly diversified demands in reliability of semiconductor devices, there is also a need for a semiconductor device that enables various burn-in tests, for example by inputting arbitrary patterns.
SUMMARY OF THE INVENTION
The present invention is accomplished in order to provide a solution to the foregoing and other problems in prior art, by providing a semiconductor device in which a data for burn-in testing from an input terminal of one scan chain can be fed to another scan chain.
The invention also provides a semiconductor device in which a data for burn-in testing that is output from one scan chain can be fed to another scan chain.
These semiconductor devices according to the invention make it possible to eliminate the foregoing limitation of the number of probes.
The invention also provides a semiconductor device in which a data for burn-in testing which is fed from each input terminal of a plurality of scan chains, or a data for burn-in testing which is output from a plurality of scan chains can be fed to other scan chains.
This configuration makes it possible to employ various patterns of data in burn-in testing.
The invention also provides a semiconductor device in which a data for burn-in testing which is fed from each input terminal of a plurality of scan chains, or a data for burn-in testing which is output from a plurality of scan chains can be fed to other plural scan chains.
This configuration also makes it possible to employ various patterns of data in burn-in testing.
A semiconductor device according to the invention in which a data for burn-in testing that is output from one scan chain can be fed to another scan chain may further comprise a delay circuit for delaying the data for burn-in testing which is output from one scan chain.
This configuration also makes it possible to employ various patterns of data in burn-in testing.
In a scan chain to which a data for burn-in testing is not supplied from a corresponding input terminal, a selector may be provided between the corresponding input terminal and the scan chain such that the data for burn-in supplied from an input terminal of another scan chain. The selector passes one of input signals to a downstream scan chain in response to an external selecting signal.
In the case where a plurality of such selectors are provided, a control circuit having an element capable of storing a state such as a flip-flop, a latch, ROM, RAM or the like may be provided to instruct each of the selectors to select an input signal. The control circuit controls selecting operation of each of the selectors in response to a selecting signal or the like which is synchronized with a clock signal.
Further, a semiconductor device according to the invention may be configured so that the selectors are connected in cascade. According to such a configuration, it is made possible to eliminate a problem of fan out, and to implement such a test that burn-in is performed in certain circuit blocks and not in other circuit blocks.
In addition, a semiconductor device according to the invention allows circuit design to be readily modified for an optimal wafer level burn-in testing.
As described above, according to the present invention, in burn-in testing with the use of scan chains, the number of input terminals used for inputting burn-in data to subject circuits can be reduced. Thereby, reduction in the number of probes for feeding burn-in data is achieved.
The invention also achieves burn-in testing in which complicated input is supplied.
In addition, since an element capable of storing a state such as flip-flop or the like is employed in the control circuit for controlling the selector, the control circuit is made simple.


REFERENCES:
patent: 5043988 (1991-08-01), Brglez et al.
patent: 5282224 (1994-01-01), Harada
patent: 5323400 (1994-06-01), Agarwal et al.
patent: 5329532 (1994-07-01), Ikeda et al.
patent: 5341096 (1994-08-01), Yamamura
patent: 5477493 (1995-12-01), Danbayashi
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