Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Including dielectric isolation means
Reexamination Certificate
2001-10-30
2003-12-09
Jackson, Jerome (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Including dielectric isolation means
C257S347000, C257S513000, C257S515000, C257S501000, C257S368000, C257S524000, C257S787000, C257S791000
Reexamination Certificate
active
06661076
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to a semiconductor device having a SOI (silicon on insulator) substrate including a semiconductor layer, on which a desired element is formed, disposed on an insulating layer which is disposed on a conductive support substrate. More specifically, the present invention relates to a semiconductor device which is a thin type, has a high breakdown voltage, and is effectively applied to a flat type display device such as a plasma display device (hereinafter referred to as a PDP device) or an electroluminescence display device (hereinafter referred to as an EL device). The present application is based on Japanese Patent Application No. 363055/2000, which is incorporated herein by reference.
2. Description of the Related Art
With respect to a flat type display device such as the PDP device or the EL device, in order to realize miniaturization, thinness, reduce power consumption or the like, a high breakdown voltage semiconductor device is used in many cases. In particular, in the case of reduced consumption power by utilizing components having low consumption power including a semiconductor device to be used, in order to suppress the consumption of reactive power by charging and discharging a large stray capacitor necessarily included in the semiconductor device structure, a power recovery circuit is provided to reduce the consumption power of the display device.
FIGS. 1A and 1B
show explanatory views of a low power driver device in a plasma display described in Japanese Patent No. 2770657. With reference to
FIG. 1A
, a low power driver device (power recovery circuit)
600
includes a capacitor CR having a sufficiently larger capacitance than a load capacitor CL, a p-channel type field effect transistor (hereinafter referred to as a pMOS)
611
and a diode D
1
, which function as a switch for charging CL from CR, an n-channel type field effect transistor (hereinafter referred to as an nMOS)
621
and a diode D
2
, which function as a switch for discharging CL, an inductor L
1
which forms a resonant circuit together with CL at charge and discharge and recovers reactive power, a pMOS
612
to maintain an output at a voltage V
0
, and an nMOS
622
to maintain an output at a ground potential. The load capacitor CL is a parasitic capacitor such as a counter capacitor or a line capacitor, which is present in the plasma display. If a drive frequency is given by f
0
, power of f
0
×CL×V
0
2
is generally wasted.
The low power driver device
600
is for recovering the wasted reactive power and operates as follows. When the output rises as shown in
FIG. 1B
, the pMOS
611
is turned on to form an equivalent circuit as shown in FIG.
2
. The output rises to V
0
by the resonant circuit composed of L
1
and CL and at the moment, the pMOS
612
is turned on and thus the output is maintained at V
0
. On the other hand, when the output falls, the nMOS
621
is turned on to construct a resonant circuit as shown in FIG.
2
. Thus, the output falls to 0 V. Also, the nMOS
622
is turned on and thus the output is maintained at 0 V. Such a series of operations is the operation of the resonant circuit and energy for charging CL is again recovered by CR. In addition, by this operation, a potential of CR is automatically maintained at V
0
/2.
When the low power driver device
600
is applied to the PDP device, for example, as shown in
FIG. 3
, an output terminal
601
is connected with a high voltage portion common power source terminal
501
of a driver IC
500
such as a scan driver circuit in the plasma display panel. The driver IC
500
supplies a high voltage V
0
inputted from the high voltage portion common power source terminal
501
from output terminals
506
a
to
506
x
to predetermined electrodes in the plasma display panel through a selection portion
510
. Reference symbol CL denotes a capacitor in the case where it is viewed from the output terminals
506
a
to
506
x
. The selection portion
510
is composed of a plurality of CMOS switch portions
511
to
51
x
. For example, the CMOS switch portion
511
connects a high voltage common wiring connected with the high voltage portion common power source terminal
501
with a ground by a serial connector made from the source drain path of a pMOS
511
P and the source drain path of an nMOS
511
N, and also connects a common connection point N
21
with the output terminal
506
a
. Although the descriptions are omitted here, the other CMOS switch portions
512
to
51
x
have the same structure. Hereinafter, the CMOS switch portion
511
will be described as an example. With such a structure, at power recovery operation for recovering charges discharged from the load capacitor CL, the charges are recovered by the capacitor CR through the output terminal
506
a
, the common connection point N
21
, and the pMOS
511
P in the driver IC
500
. With this structure, when the driver IC is formed on a general silicon substrate with a self-isolation structure, an element cross sectional structure as shown in
FIG. 4A
is obtained (equivalent circuit is shown in FIG.
4
B). Thus, a leak current Ir is produced through a P-type substrate
830
and an N-well parasitic bipolar transistor
891
, which causes a reduction in power recovery efficiency. On the P-type substrate
830
, P-type diffusion layers
836
and
832
, N-type diffusion layers
831
and
833
, and insulating layers
842
are formed. On the other hand, when it is formed on an SOI substrate with a trench isolation structure, an element cross sectional structure as shown in
FIG. 5A
is obtained (equivalent circuit is shown in FIG.
5
B). Thus, there is an advantage in which all charges discharged from the load capacitor CL can be recovered by the capacitor CR. Therefore, in a high breakdown voltage semiconductor device including a display device driver IC, the SOI substrate is used as a chip substrate in many cases. On a silicon substrate
301
, an insulating layer
302
, and a semiconductor layer having P-type diffusion layers
353
, N-type diffusion layers
356
and isolation trenches
315
are formed.
In addition to realizing lower consumption power of the display device, in order to progress miniaturization and decrease in thickness thereof, miniaturization and decrease in thickness of a semiconductor device to be used in large quantity as a driver circuit is essential. Also, with the driver circuit, mounting to a thin type package such as a TCP (tape carrier package) and coping with a bare chip assembly such as a flip chip assembly and are desirable. In mounting to the thin type package, the flip chip assembly, or the like, for example, as shown in
FIGS. 16A and 16B
, generally, a rear surface
806
(surface on which an element is not formed) of a semiconductor chip
800
is not connected with another conductor such as an island and thus becomes a floating state. Thus, when the SOI substrate is used as a chip substrate, generally, a conductive support substrate becomes a floating state. Therefore, if a conductive support substrate
801
becomes a floating state in the chip
800
using the SOI substrate as the chip substrate, the potential of the conductive support substrate
801
becomes unstable. Also, as disclosed in, for example, Japanese Patent No. 2654268 or Japanese Patent No. 3061020, an inverse breakdown voltage of a p-n junction formed in a semiconductor layer
803
on the SOI substrate is changed dependent on the potential of the conductive support substrate
801
. Thus, if the conductive support substrate
801
becomes a floating state and its potential cannot be maintained at a suitable value, a problem such as the inverse breakdown voltage is greatly decreased is caused. Thus, the chip using the SOI substrate has been mounted on a package having an island such as a general lead frame. However, mounting the chip using the SOI substrate to the package including the TCP and an applying the chip using the same to the flip chip assembly, in which the rear surface of the
Takasugi Kazunari
Toeda Masahiro
Jackson Jerome
NEC Electronics Corporation
Nguyen Joseph
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