Semiconductor device

Details Semiconductor device Semiconductor device

2001-11-19

2003-08-12

Wojciechowicz, Edward (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Regenerative type switching device

Combined with field effect transistor

C257S335000, C257S336000, C257S338000

Reexamination Certificate

active

06605829

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and, more particularly, a semiconductor device built in a discrete device or an IC (Integrated Circuit).
2. Description of the Background Art
FIG. 7
is a cross section schematically showing the configuration of a semiconductor device of a first conventional technique. Referring to
FIG. 7
, a DMOS (Double diffused Metal Oxide Semiconductor) transistor is formed in a semiconductor substrate. This DMOS transistor has, mainly, an n
−
layer
101
, an n
+
layer
102
, a p-type diffusion region
103
, an n
+
diffusion region
105
, a gate insulating layer
112
, and a gate electrode layer
106
.
n
−
layer
101
is formed deeply from a first main surface of the semiconductor substrate toward a second main surface side. p-type diffusion region
103
is formed so as to be in contact with n
−
layer
101
in the first main surface. In the first main surface in p-type diffusion region
103
, n
+
diffusion region
105
is formed so as to be adjacent to p
+
diffusion region
104
.
Gate electrode layer
106
is formed on the first main surface so as to face p-type diffusion region
103
sandwiched between n
−
layer
101
and n
+
diffusion region
105
via gate insulating layer
112
. An insulating layer
113
is formed so as to cover gate electrode layer
106
, and a source electrode
108
is formed so as to be connected to n
+
diffusion region
105
and p
+
diffusion region
104
which are exposed from insulating layer
113
.
On the second main surface side of p-type diffusion region
103
, n
−−
layer
107
is formed so as to be in contact with n
−
layer
101
. n
−−
layer
107
has impurity concentration lower than that of n
−
layer
101
. n
+
layer
102
is formed on the second main surface side of n
−
layer
101
and n
−−
layer
107
, and a drain electrode
109
is formed so as to be connected to n
+
layer
102
.
In the first conventional technique, as shown in
FIG. 8
, n
−
layer
101
is formed so that its cross-sectional area in the lateral direction of the drawing is decreased from the source electrode side (first main surface side) toward the drain electrode side (second main surface side). n
−−
layer
107
is formed so that its cross-sectional area in the lateral direction of the drawing increases by the same amount.
In the structure, when each of the source and gate is set to 0V and a positive bias is applied to the drain, the DMOS transistor enters a withstand checking state. At this time, a depletion layer extends, as shown by a dotted line in
FIG. 8
, in the entire area of n
−
layer
101
and n
−−
layer
107
and a part of each of p-type diffusion are
103
and n
+
layer
102
which are in contact with n
−
layer
101
and n
−−
layer
107
.
Assuming now that the cross-sectional area in the lateral direction of the drawing of n
−
layer
101
decreases with an exp curve (exponential function curve), the concentration in n
−−
layer
107
is sufficiently low, and the electric line of force hardly enters n
−−
layer
107
side and that the electric field is uniform in the cross section in the lateral direction of the drawing of n
−
layer
101
, the electric field in the cross section in a position (x) is derived by the following equation 1.
E
(
x
)=(
q
/&egr;)·{
aN
(exp(
bx
)−1)/
b+M}/{a
(exp(
bx
))}  (Equation 1)
In the equation 1, q denotes an electronic charge, N indicates impurity concentration of n
−
layer
101
, &egr; indicates a dielectric constant of silicon (Si), and M represents the number of space charges in n
+
layer
102
. The position (x) denotes a distance between the junction of n
−
layer
101
and n
+
layer
102
and the source side.
When the relation of M=aN/b (equation 2) is satisfied in the equation 1, the equation 1 is expressed by the following equation 3.
E
(
x
)=
qN
/(&egr;
b
)  (equation 3)
By the equation 3, the electric field E(x) in the cross section in the lateral direction of
FIG. 8
becomes always constant irrespective of the position (x). In the normal structure (structure in which there is no n
−−
layer
107
in
FIG. 7
but n
−
layer
101
is formed on the entire face), a step junction is formed. Consequently, the electric field decreases monotonously with distance from the source side toward the drain side. In contrast, in the structure shown in
FIG. 7
, a constant electric field can be obtained, so that n
−
layer
101
can be made thinner than that in the normal structure. As a result, by a trade-off between a withstand voltage and ON-state resistance (effective on-state resistance), the technique can exceed the limit of the normal structure.
In the first conventional technique, the cross-sectional area in the lateral direction of the drawing of n
−
layer
101
decreases with distance from the source side toward the drain side. Consequently, there is a structural optimum value in the relation with the resistance in n
−
layer
101
. The resistance in the direction from the source side toward the drain side in the first conventional technique is obtained by the following equation 4. Specific resistance of n
−
layer
101
is similar to &agr;/N.
R=&agr;/N·∫
1
/a
·exp(−
bx
)
dx=&agr;/Nab
·(1−exp(−
bl
))  (equation 4)
&agr; in the equation 4 denotes a factor of proportionality of the specific resistance and impurity concentration. In the equation 4, to reduce the resistance, it is optimum that there is no n
−−
layer
107
on the source side and n
−
layer
101
is formed in the entire surface. Consequently, effective ON-state resistance RS becomes the minimum in the following equation.
RS=R·a
·exp(
bl
)=&agr;/(
Nb
)·(exp(
bl
)−1)
From the equation 3, N/b is a constant. When N/b is set as &bgr;, the effective ON-state resistance RS is expressed as the following equation 5.
RS
=&agr;·&bgr;/(
N·N
)·(exp(
Nl
/&bgr;)−1)  (equation 5)
Since the function becomes the minimum when Nl/&bgr;≈1.6, the optimum impurity concentration N which minimizes the effective ON-state resistance RS exists, and the result b is also determined. Therefore, the optimum value exists in the entire structure.
A second conventional technique will be described as another technique.
FIG. 9
is a cross section schematically showing the configuration of a semiconductor device in the second conventional technique. Referring to
FIG. 9
, in the second conventional technique, in place of n
−−
layer
107
shown in
FIG. 7
, a p
−
layer
110
is formed. The pn junction between p
−
layer
110
and n
−
layer
101
extends almost in the direction perpendicular to the first and second main surfaces of the semiconductor substrate (thickness direction). The impurity concentration of p
−
layer
110
and that of n
−
layer
101
are controlled to be the same, thereby obtaining the same effect as that of the first conventional technique.
Since the configuration other than the above is substantially the same as that of the above-described first conventional technique, the same components are designated by the same reference numerals and their description will not be repeated.
In the second conventional technique, by providing p
−
layer
110
, the electric line of force from the space charge of n
−
layer
101
enters p
−
layer
110
side at a predetermined rate. Consequently, as the electric line of force extends from the drain side toward the source side, it extends from the inside of n
−
layer
101
and gradually enters p
−
layer
110
side, so that the electric field in n
−
layer
101
is maintained to be const

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