Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Passive components in ics
Reexamination Certificate
2001-05-07
2003-04-15
Flynn, Nathan J. (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Passive components in ics
C257S202000, C257S209000, C257S528000, C438S132000, C438S215000, C438S281000
Reexamination Certificate
active
06548884
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to semiconductor devices and more particularly to a semiconductor device having fuse state determination circuitry.
BACKGROUND OF THE INVENTION
Semiconductor devices can use fuse structures than are programmable during the manufacturing process. One such application for a fuse structure is in a semiconductor memory device. In a semiconductor memory device, tight processing margins can cause defects to arise in a memory array. The semiconductor memory will be tested for defects and when there are defects, redundant memory cells can be used to replace defective bits of the memory array. The redundancy will typically be in the form of a redundant row or a redundant column of memory cells.
In order to program the redundant row or column to respond to the address value of a defective bit or bits, fuse structures will be programmed with the address value corresponding to the defective bit. In this case a fuse corresponding to one address bit will be left intact to create a short fuse condition for one address value and will be broken (blown) to create an open fuse condition for another address value. In this manner a redundant decoder can be programmed to respond to the address value corresponding to the defective memory cell or cells.
Referring now to
FIG. 7
, a circuit diagram of a conventional fuse circuit is set forth and given the general reference character
700
. Conventional fuse circuit
700
has two fuses (F
701
and F
702
) connected in series between a power supply voltage VCC and ground. Fuse F
701
and fuse F
702
are connected at a connecting point. Conventional fuse circuit
700
also has an inverter IV
701
having an input connected to the connecting point of fuses (F
701
and F
702
) and an output generating a logic value corresponding to the programmed configuration of fuses (F
701
and F
702
).
When fuse F
701
is broken, the input of inverter IV
701
becomes a logic low thus generating a logic high output. When fuse F
702
is broken, the input of inverter IV
701
becomes a logic high thus generating a logic low output.
Conventional fuse circuit
700
requires two fuses (F
701
and F
702
) for one programmable bit. Each fuse (F
701
and F
702
) requires significant circuit area due to the accuracy and destructiveness of the fuse breaking (blowing) procedure. Thus, conventional fuse circuit
700
consumes significant chip area, which increases manufacturing costs. Furthermore, there are typically many fuse circuits on a chip.
Also, conventional fuse circuit
700
consumes significant amounts of current before a fuse (F
701
or F
702
) is broken. This is undesirable because the increased current consumption can cause the chip to operate differently in the test condition than it would in a normal operating condition. This can create testing integrity problems.
Another drawback with conventional fuse circuit
700
is that a fuse (F
701
and F
702
) must be broken for each conventional fuse circuit
700
on the chip regardless as to whether there are any defects. Otherwise, operating current would be undesirably high.
In order to address some of the above-mentioned problems, other fuse circuit configurations have been developed.
Referring now to
FIG. 8
, a conventional fuse evaluation circuit including fuses is set forth in a schematic diagram and given the general reference character
800
.
Conventional fuse evaluation circuit
800
has a reference voltage generation circuit
810
and a fuse circuit
820
.
Fuse circuit
820
has a single fuse F
801
and transistor T
801
. Fuse F
801
is connected between a power supply VCC and a connecting node N
801
. Transistor T
801
has a source/drain path connected between ground and connecting node N
801
. A control gate of transistor T
801
receives a reference voltage VG
8
from reference voltage generation circuit
810
. Fuse circuit
820
also has a latch circuit L
822
connected to connecting node N
801
.
Reference voltage generation circuit
810
has an inverter IV
810
connected to receive a fuse evaluation signal S
801
and has an output connected to control gates of p-channel transistor MP
801
and n-channel transistor MN
802
. Reference voltage generation circuit
810
has a constant-current source
1801
connected between a power supply VCC and the source of p-channel transistor MP
801
. P-channel transistor has a drain connected to reference voltage VG
8
. Reference voltage generation circuit
810
also has a n-channel transistor MN
801
having a drain and a gate connected to reference voltage VG
8
and a source connected to ground. N-channel transistor MN
802
has a drain connected to reference voltage VG
8
and a source connected to ground.
Reference voltage generation circuit
810
receives a fuse evaluation signal S
801
and generates a reference voltage VG
8
. Fuse circuit
820
receives the reference voltage and evaluates the condition of fuse F
801
.
When fuse evaluation signal S
801
is logic low, the output of inverter IV
810
becomes high, thus p-channel transistor MP
801
is turned off and n-channel transistor MN
802
is turned on. Thus, reference voltage generation circuit
810
provides a reference voltage VG
8
that is at ground. This turns off transistor T
801
, which reduces the standby current consumption in fuse circuit
820
.
When the status of fuse F
801
is to be evaluated, evaluation signal S
801
transitions from logic low to logic high. Inverter IV
810
provides logic low to the control gates of p-channel transistor MP
801
and n-channel transistor MN
802
. Thus, p-channel transistor MP
801
is turned on and n-channel transistor MN
802
is turned off. This allows constant current source
1801
to provide a current through p-channel transistor and n-channel transistor MN
801
to ground. N-channel transistor MN
801
is configured in a diode configuration to provide a reference voltage VG
8
to the control gate of transistor T
801
in fuse circuit
820
. In this manner, transistor T
801
is turned on and the level of reference voltage VG
8
and size of transistor T
801
is chosen so that transistor T
801
provides an on-impedance path that has a resistance that is approximately two times larger than the intact resistance of fuse F
801
. Latch circuit L
801
includes an inverter to receive the voltage at connecting node N
801
. The threshold of the inverter is VCC/2. Thus, if the potential of connecting node N
801
is less than VCC/2, fuse F
801
is evaluated as broken and a low logic level is latched in latch circuit L
822
. If the potential of connecting node N
801
is greater than VCC/2, fuse F
801
is evaluated as intact and a high logic level is latched in latch circuit L
822
. The potential of connecting node N
801
is determined by the ratio of the on-resistance of transistor T
801
and the resistance of intact or broken fuse F
801
.
However, a fuse such as fuse F
801
is typically blown by a laser and is not always completely broken. A fuse F
801
is sometimes only partially broken which can cause the fuse F
801
to have a resistance in the range of several tens of k&OHgr;. In a case in which conventional fuse evaluation circuit
800
is used, the resistance of a partially broken fuse can cause the potential of connecting node N
801
to be very close to VCC/2 during the fuse evaluation. This can create cases where fuse F
801
may be evaluated to be broken under a certain operating condition, but with a variation in temperature or voltage, the on-resistance of transistor T
801
may vary enough to allow the fuse F
801
to be evaluated as intact and vice-versa. Furthermore, when a fuse F
801
is partially broken, the resistance may change over time allowing inconsistent evaluations.
Semiconductor devices must be screened during the manufacturing stage to ensure that only passing units are sold to the customer. However, if there are fuse evaluations that indicate a passing condition during testing only to fail at a later time, then the screening process has been inadequate. Thus, it is necessary to properly evaluate partially broken f
Flynn Nathan J.
Forde Remmon R.
NEC Corporation
Sako Bradley T.
Walker Darryl G.
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