Active solid-state devices (e.g. – transistors – solid-state diode – Physical configuration of semiconductor – With peripheral feature due to separation of smaller...
Reexamination Certificate
2001-07-02
2003-08-12
Jackson, Jerome (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Physical configuration of semiconductor
With peripheral feature due to separation of smaller...
C257S762000
Reexamination Certificate
active
06605861
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a manufacturing method thereof, and more specifically to, for example, a structure of a scribe line area in an integrated circuit and a manufacturing method thereof.
2. Description of the Background Art
FIGS. 23
to
26
are schematic cross-sectional views that show a sequence of processes of a manufacturing method of a conventional semiconductor device, for example, described on page 107 in “Monthly Semiconductor World”, December Issue, 1997. Referring to
FIG. 23
, a resist pattern
120
is formed on an insulating film
102
by a photolithographic technique. This insulating film
102
is subjected to a reactive ion etching process by using this resist pattern
120
as a mask. Thus, a groove
102
a
is formed on the insulating film
102
. Thereafter, the resist pattern
120
is removed by ashing and a chemical treatment.
Referring to
FIG. 24
, a TaN film is formed on the insulating film
102
having a groove
102
a
as a barrier metal
114
with a thickness of 50 nm, and a Cu film is further formed thereon with a thickness of 150 nm as a seed layer
112
a
for a plated film.
Referring to
FIG. 25
, in a plating liquid of a copper sulfate bath, an electrolytic plating process is carried out so that the groove
102
a
is filled with the Cu film
112
. Thereafter, the Cu film
112
and the barrier metal
111
are abraded and removed by a chemical and mechanical polishing method (CMP method), until at least the upper surface of the insulating film
102
has been exposed.
Referring to
FIG. 26
, by this CMP method, the Cu film
112
and the barrier metal
111
remain only in the groove
102
a
to form wiring.
FIG. 27
is a schematic cross-sectional view that shows the structure of an electrolytic plating device, for example, shown on page 470 of “Proc. Of 1993 VLSI Multilevel Interconnection Conference”. Referring to
FIG. 27
, the electrolytic plating is carried out by applying a voltage between an anode
132
and a wafer
110
that are placed in an electrolytic solution
135
in a plating vessel
133
; thus, a Cu film is deposited on the wafer
110
side. Here, the electrolytic solution
135
is introduced into the plating vessel
133
from an electrolytic solution inlet
134
, and discharged from an electrolytic solution outlet
136
.
On the wafer
110
, the barrier metal
111
and the seed layer
112
a
have been formed on the insulating film
102
, and the plated Cu film is deposited on the seed layer
112
a
. Here, the insulating film
102
is formed on, for example, a semiconductor substrate
103
.
Moreover, the voltage to be applied to the wafer
110
is supplied to the barrier metal
111
and the seed layer
112
a
on the surface of the wafer
110
through a contact electrode
131
. At this time, the deposition of the plating film preferentially takes place in the groove and on the bottom of the hole because of the effects of an additive agent added to the electrolytic solution
135
so that it is possible to obtain a superior filling property. Since such a phenomenon continues even after the groove and the hole have been filled, as the plating time becomes longer, the plated film tends to form a rise at the portions of the groove and the hole.
As described above, since the film deposition preferentially takes place in the groove and on the bottom of the hole in the electrolytic plating, the plated film tends to form a rise at the portions of the groove and the hole as the plating proceeds. Such a rise is high on the periphery of the wafer
110
, and low in the center portion. The reason for this phenomenon is explained as follows:
In the electrolytic plating, a voltage is applied between the wafer
110
and the anode
132
so that a plating film is deposited on the seed layer
112
a
. The peripheral portion of the wafer
110
is in contact with the contact electrode
131
with the voltage being applied thereto.
Here, the thickness of the barrier metal
111
and the seed layer
112
a
is extremely thin and has very high resistance, with the result that the seed layer
112
a
comes to have an electric potential distribution in accordance with the distance from the contact electrode
131
.
As described above, the deposition rate is higher on the peripheral portion of the wafer
110
close to the contact than that in the center portion at the initial stage of plating. Such a difference in the deposition rate is great in the case when the thickness of the plated Cu film formed on the wafer
110
is small. In other words, the difference in the deposition rate is the greatest at the initial stage of plating, and becomes smaller as the thickness of the plated film becomes greater.
In the case when the Cu film is removed by the CMP method, the abrasion time is set so as to remove the peripheral raised portion, with the result that the groove in the center portion and the hole portion tend to be excessively abraded, causing a problem in that a concave dent is formed on the surface of the Cu film (that is, on the surface of the wiring). The resulting problems are that there is an increase in the wiring resistance and that there are great deviations in the wiring resistance.
Moreover, when such a concave dent is formed on the wiring surface, metal tends to remain in a concave section on a upper wiring layer formed thereon, resulting in a problem of short-circuiting in the wiring.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a semiconductor device and a manufacturing method thereof, which can reduce a difference in the deposition rate of plating between the center portion and the peripheral portion on a substrate.
A semiconductor device in accordance with one aspect of the present invention is provided with a plurality of chip-use element formation areas, each having a conductive layer formed by a plating method, a scribe line areas for dividing the plurality of chip-use element formation areas, and an interconnections being formed in the scribe line area and extended to the vicinity of an end edge of a wafer.
In the semiconductor device in accordance with this aspect of the present invention, the interconnection is formed from the vicinity of end edge of the wafer to which a contact electrode for supplying a voltage to the wafer at the time of plating is connected, to the inside of the scribe line area. The formation of the interconnection in this type makes it possible to reduce the resistance in comparison with a case in which only a thin seed layer and a barrier metal are formed; therefore, it becomes possible to reduce a difference in the electric potential between the center portion of the wafer and the peripheral portion thereof to which the contact electrode is connected. Consequently, the difference in the plating rate between the center portion and the peripheral portion of the wafer at the initial stage of plating, thereby enabling to reduce the occurrence of a dent on the surface of the upper-layer interconnection after the CMP process.
In the above-mentioned aspect, more preferably, the interconnection is formed in a manner so as to extend from side of a first chip-use element formation area to side of a second chip-use element formation area.
In this manner, each interconnection is extended laterally through the scribe line area located beside each chip-use element formation area so that the resistance reducing effect is further improved.
In the above-mentioned aspect, more preferably, the interconnection is allowed to surround the chip-use element formation area.
In this manner, the interconnection is extended and located in a manner so as to surround the periphery of each chip-use element formation area so that the resistance reducing effect is further improved.
In the above-mentioned aspect, more preferably, a test element for testing the characteristics of the element within the chip-use element formation area is further provided, and the test element is placed on the scribe line area.
In this manner, the present invention
Jackson Jerome
Leydig , Voit & Mayer, Ltd.
Mitsubishi Denki & Kabushiki Kaisha
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