Semiconductor device

Details Semiconductor device Semiconductor device

2002-06-27

2003-05-20

Hoang, Huan (Department: 2818)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185170, C365S189070

Reexamination Certificate

active

06567309

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2000-288329, filed Sep. 22, 2000, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device comprising a voltage boosting circuit for boosting the power supply voltage, particularly, to a semiconductor device comprising a voltage boosting circuit that is boost-driven by a plurality of phase shifted clock signals generated from an oscillation circuit, the semiconductor device being used in, for example, a semiconductor memory device in which a high voltage used in erasing, writing and reading data in and from the memory cell is generated from a voltage boosting circuit.
2. Description of the Related Art
FIG. 1
is a cross sectional view showing the construction of one memory cell included in a flash memory, which is one of semiconductor memory devices. As shown in
FIG. 1
, an N-well
2
is formed in a P-type semiconductor substrate
1
. Further, a P-well
3
is formed in the N-well
2
. Source and drain regions
4
,
5
each consisting of an N
+
region are formed apart from each other in the P-well
3
. A floating gate
6
is formed on the channel region between the source and drain regions
4
and
5
with an insulating film (not shown) interposed between the floating gate
6
and the channel region. Further, a control gate
7
is formed on the floating gate
6
with an insulating film (not shown) interposed therebetween.
A contact region
8
consisting of a P
+
region is formed on the P-type semiconductor substrate
1
. A contact region
9
consisting of an N
+
region is formed in the N-well
2
. Further, a contact region
10
consisting of a P
+
region is formed in the P-well
3
.
During the operation, a gate voltage Vg is supplied to the control gate
7
of the memory cell, a drain voltage Vd is supplied to the drain region
5
, and a source voltage Vs is supplied to the source region
4
. Also, a voltage equal to the source voltage Vs is supplied to each of the contact regions
9
and
10
, and a ground voltage of 0V is supplied to the contact region
8
.
The memory cell shown in
FIG. 1
stores “1” level and “0” level of the data depending on the amount of electrons stored in the floating gate
6
. Also, the threshold voltage as viewed from the control gate
7
is changed in accordance with the level of the stored data. A memory cell array is formed by arranging a plurality of memory cells of the particular construction.
FIG. 2
exemplifies a circuit of a memory cell array of a NOR type flash memory. A plurality of memory cells MC are arranged in rows and columns. The control gates of the memory cells MC arranged in the same row are commonly connected to the corresponding single word line selected from a plurality of word lines WL
0
to WLn. Also, the drain regions of the memory cells MC arranged in the same column are commonly connected to the corresponding single bit line selected from a plurality of bit lines BL
0
to BLm. In general, the memory cell is divided into a plurality of blocks, and the source regions of the memory cells MC in the same block are commonly connected to the source line of the corresponding block selected from a plurality of source lines SLi.
FIG. 3
is a graph showing the relationship between the gate voltage supplied to the control gate of the memory cell during operation of the flash memory shown in FIG.
2
and the drain current flowing into the drain region of the memory cell during operation of the flash memory shown in FIG.
2
. In this case, the state that a relatively large amount of electrons are stored in the floating gate, i.e., the state that the threshold voltage Vth of the memory cell is high, represents “0” data, and the memory cell storing the “0” data is called “0” cell. On the other hand, the state that a relatively small amount of electrons are stored in the floating gate, i.e., the state that the threshold voltage Vth is low, represents “1” data, and the memory cell storing the “1” data is called “1” cell.
FIG. 4
exemplifies the values (bias conditions) of the gate voltage Vg, the drain voltage Vd and the source voltage Vs supplied to the memory cell during operation, i.e., during reading, writing and erasing of data, of the flash memory shown in FIG.
2
.
When data is read, the gate voltage Vg, the drain voltage Vd and the source voltage Vs are set at 5V, 1V and 0V, respectively. During the data writing (during the programming), the gate voltage Vg and the source voltage Vs are set at 9V and 0V, respectively. On the other hand, the drain voltage Vd is set at 5V when it comes to the memory cell in which the “0” data is written, and is set at 0V when it comes to the other memory cell, i.e., the memory cell in which the original “1” data is stored. Further, in the erasing step, the gate voltage Vg and the source voltage Vs are set at −7V and 10V, respectively, and the drain voltage Vd is put in the floating state.
The reading of data is judged depending on the state as to whether or not a cell current flows at the time when a gate voltage Vread (5V in this case) is supplied to the control gate under the state that a predetermined voltage (1V in this case) is supplied to the drain region. The judgment is performed by the comparison with the reference current Iref flowing into the reference cell, the comparison being performed by a sense amplifier (not shown).
The erasure is collectively performed in a plurality of memory cells sharing the P-well
3
shown in FIG.
1
. In the erasing step, electrons flow from the floating gate
6
into the P-well region
3
by the Fowler-Nordheim (F•N) tunneling phenomenon, with the result that all the memory cells to be erased are put in the conditions of “1” cell.
The writing is performed for each memory cell. The bit line of the memory cell in which the “0” data is written is biased to 5V so as to inject the high energy electrons generated by the channel hot electron phenomenon into the floating gate
6
. In this case, the bit line of the “1” cell, in which the original “1” data is desired to be maintained, is set at 0V. As a result, the electron injection into the floating gate
6
does not take place in the memory cell in which the data is not written, with the result that the threshold voltage Vth is not changed.
Also, a write verify operation and an erase verify operation are performed in the flash memory in the writing step and the erasing step in order to confirm the degree of writing and erasing. In the write verify operation, the voltage of the control gate
7
is set at a high voltage Vpv, e.g., 7V, compared with the voltage Vread in the reading step (5V in this case), so as to perform the “0” read operation. The write operation and the write verify operation are alternately performed repeatedly, and the write operation is finished when all the data of the memory cells in which the data is written have become “0”.
In the erasing step, the voltage of the control gate
7
is set at a voltage Vev, e.g., 3.5V, which is lower than the voltage Vread in the reading step, so as to perform the “1” read operation. The erase operation and the erase verify operation are alternately performed repeatedly, and the erase operation is finished when all the data of the memory cells to be erased have become “1”. As a result, the cell current Icell is secured sufficiently.
As described above, the voltage supplied to the control gate of the memory cell is changed variously in accordance with the operation mode. For example, the voltage noted above is changed to 9V, 7V, 5V, and 3.5V. The voltages of 9V, 7V and 5V are higher than the power supply voltage supplied from the outside.
In order to form various voltages such as 9V, 7V and 5V, which are higher than the power supply voltage supplied from the outside, a required number of boosting circuits for boosting the power supply voltage are arranged, and

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