Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing
Reexamination Certificate
2001-10-16
2003-07-01
Cunningham, Terry D. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Synchronizing
C327S543000
Reexamination Certificate
active
06586975
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The present invention generally relates to technology for a semiconductor device, and more particularly, to a start-up circuit included a constant current circuit.
This application is a counterpart of Japanese patent application, Serial Number 317914/2000, filed Oct. 18, 2000, the subject matter of which is incorporated herein by reference.
Description of the Related Art
A conventional semiconductor device is disclosed as shown in
FIGS. 5-6
.
FIG. 5
is a circuit diagram showing the conventional semiconductor device.
FIG. 6
is a chart showing a change of a power supply voltage level and a voltage level at a node N
3
.
The conventional semiconductor device comprises a node N
1
being supplied with a power supply voltage VDD, a node N
2
being supplied with a ground voltage GND, a resistor R
1
, a current mirror circuit
501
, a current mirror circuit
502
and a start-up circuit
503
. The current mirror circuit
501
comprises an input terminal
501
I, an output terminal
501
O, PMOS transistor (P-channel MOSFET) T
1
and PMOS transistor T
2
. The gate electrodes of PMOS transistors T
1
and T
2
are connected to each other. The current mirror circuit
502
comprises an input terminal
502
I, an output terminal
502
O, NMOS transistor (N-channel MOSFET) T
3
and NMOS transistor T
4
. The gate electrodes of NMOS transistors T
3
and T
4
are connected to each other. The resistor R
1
has two terminals, one of which is connected to the current mirror circuit
502
and the other of which is connected to the node N
2
. The conventional start-up circuit
503
comprises a node N
3
, PMOS transistor T
5
, a resistor R
2
and a capacitor C
1
. PMOS transistor T
5
has a gate electrode connecting to the node N
3
, a source electrode connecting to the node N
1
and a drain electrode connecting to an input terminal
502
I of the current mirror circuit
502
. PMOS transistor T
5
is in an ON state when the gate electrode thereof has a second voltage. PMOS transistor T
5
is in an OFF state when the gate electrode thereof has a first voltage. The resistor R
2
has two terminals, one of which is connected to the node N
1
and the other of which is connected to the node N
3
. The capacitor C
1
has two terminals, one of which is connected to the node N
3
and the other of which is connected to the node N
2
.
Next, the operation of the conventional semiconductor device will be described as follows.
When power turns on in the conventional semiconductor device, the voltage on the node N
3
is the second voltage. At this time, the voltage on the gate electrode of PMOS transistor T
5
also is the second voltage. A current path occurs between the source electrode and the drain electrode of PMOS transistor T
5
. Therefore, a current path occurs between the power supply voltage node VDD and the input terminal
502
I through PMOS transistor T
5
. The voltage on the gate electrode of NMOS transistor T
3
increases. A current path occurs between the input terminal
502
I and the ground voltage GND. Since the gate electrodes of NMOS transistors T
3
and T
4
are connected to each other, the gate electrode of NMOS transistor T
4
increases. A current path occurs between the output terminal
502
O and the ground voltage GND. The voltage on the gate electrode PMOS transistor T
1
decreases. A current path occurs between the power supply voltage VDD and the input terminal
501
I. Therefore, a current path occurs between the power supply voltage VDD and the ground voltage GND through PMOS transistor T
1
and NMOS transistor T
4
. Since the gate electrodes of PMOS transistors T
1
and T
2
are connected to each other, the gate electrode of PMOS transistor T
2
decreases. A current path occurs between the power supply voltage VDD and the output terminal
501
O. Therefore, a current path occurs between the power supply voltage VDD and the ground voltage GND through PMOS transistor T
2
and NMOS transistor T
3
.
On the other hand, the voltage level on the node N
3
gradually increases to the first voltage. PMOS transistor T
5
goes into the OFF state. Therefore, a current path between the power supply voltage node VDD to the input terminal
502
I through PMOS transistor T
5
is cut off. However, the conventional semiconductor device operates stably, because current at the input terminals
501
I and
502
I has already begun flowing.
As shown in FIG.
6
(A), when an increase (a solid line) in the power supply voltage VDD occurs faster than an increase (a dotted line) in the voltage on the node N
3
(speed determined by a time constant of the resistor R
2
and the capacitor C
1
), the potential difference occurs between the power supply voltage VDD (the source electrode of PMOS transistor T
5
) and the node N
3
(the gate electrode of PMOS transistor T
5
). The potential difference lets the current path between the source and drain electrodes of PMOS transistor T
5
occur.
However, as shown in FIG.
6
(B), when an increase (a solid line) in the supply voltage VDD occurs slowly (in other words, when the voltage level of the power supply voltage VDD increases with an increase in the time constant), the potential difference which lets the current path between the source and drain electrodes of PMOS transistor T
5
occur does not occur. Therefore, the conventional semiconductor device can not work. To solve the above problem, there is a measure which lets the resistance value of the resistor R
2
be high and which lets the capacitance the capacitor C
1
be large. At this time, to obtain a desired increase in speed of the power supply voltage VDD, which is 500 ms (microsecond), the semiconductor device must have the resistor R
2
, the resistor value of which is
5
G &OHgr; (gigaohm) and the capacitor C
1
, the capacitance of which is 100 PF (picofarad).
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a semiconductor device that may be driven stably even if the increase in speed of the supply voltage changes.
It is another object of the present invention to provide a semiconductor device that may be driven by low current.
It is another object of the present invention to provide a semiconductor device that may be driven by low voltage.
It is further object of the present invention to provide a semiconductor device that may be driven at fast speed.
According to one aspect of the present invention, for achieving the above object, there is provided a semiconductor device, with a first node which has a first voltage; a second node which has a second voltage, wherein the second voltage is lower than the first voltage; a first current mirror circuit which has an input terminal and an output terminal, wherein the first current mirror circuit is coupled with the first node; a second current mirror circuit which has an input terminal and an output terminal, wherein the input terminal of the second current mirror circuit is coupled with the output terminal of the first current mirror circuit, wherein the output terminal of the second current mirror circuit is coupled with said input terminal of the first current mirror circuit and wherein the second current mirror circuit is coupled with said second node; and a start-up circuit which comprises a third node, a first switch which electrically connects the first node and the input terminal of the second mirror circuit based on a voltage level at the third node, a second switch which electrically connects the first node and the third node based on a voltage level at the input terminal of the first current mirror circuit, and a third switch which electrically connects the first node and the third node based on an inverted voltage of the voltage level at the third node.
The above and further objects and novel features of the invention will more fully appear from the following detailed description, appended claims and the accompanying drawings.
REFERENCES:
patent: 5528182 (1996-06-01), Yokosawa
patent: 5969549 (1999-10-01), Kim et al.
patent: 6060918 (2000-05-01), Tsuchida et al.
patent: 6-59761 (1994-0
Nagaya Masafumi
Nakajikkoku Masahiko
Cunningham Terry D.
Nguyen Long
Oki Electric Industry Co. Ltd.
Rabin & Berdo P.C.
LandOfFree
Semiconductor device does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor device will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3038530