Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Junction field effect transistor
Reexamination Certificate
2000-03-08
2003-04-29
Thomas, Tom (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Junction field effect transistor
C257S272000, C257S277000, C257S264000, C438S189000, C438S190000, C438S309000
Reexamination Certificate
active
06555857
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device, more particularly, a semiconductor device that is suitable for use in connecting with electric condenser microphones.
2. Description of the Related Art
A condenser microphone (ECM) is an operational element for converting air vibrations, such as voice speech, into electrical signals in accordance with changes in capacitance between electrodes. Output signals from condenser microphones are extremely weak, so that it is necessary for an amplifying element, for amplifying the output signals from a condenser microphone, to have high input impedance, high gain and low noise.
Semiconductor devices suitable for such applications include junction type field-effect-transistors (J-FET) and metal-oxide-semiconductor (MOS) type FETS. The J-FET has an advantage that the device can be readily produced in a bipolar-type integrated circuit (BIP-IC), as reported in a laid-open Japanese Patent Publication 58-197885, for example.
FIG. 1
shows an example of the structure of the J-FET device (p-channel type). An n-type epitaxial layer
2
is deposited on top of a p-type semiconductor substrate
1
. An n-type buried layer
3
is formed between the layers
1
and
2
. An island region
5
is formed by the p
+
-type separation regions
4
surrounding the buried layer
3
so as to connect the surface of the epitaxial layer
2
through to the substrate
1
.
An n
+
-type top gate region
6
is formed on the surface of the island region
5
, and a p-type channel region
7
is formed in the lower layer of the top gate region
6
. A p
+
-type source region
8
and a p
+
-type drain region
9
are formed, respectively, at each end of the channel region
7
, and gate contact regions
10
of a high n-dopant concentration are formed on each respective outer region.
Finally, a p-channel type J-FET is produced by fabricating a source electrode
11
S, a drain electrode
11
D and a gate electrode
11
G with an intervening insulation layer
16
. Utilizing the p-n junction formed in the gate region, and reverse-biasing this region, controls the strength of the depletion layer thereby controlling the drain current.
When such a circuit configuration is integrated, a p-type base region
12
, an n
+
type emitter region
13
and an n
+
type collector region
14
are formed in the other island region
5
, so that an integrated circuit network comprised by the n-p-n transistors and so on, amplifies signals received in the J-FET device.
However, to use such a device for amplifying signals from an electric condensers microphone, it is necessary, in some cases, to provide an expansion electrode
15
of an area much larger than the area of the electrode pads (bonding pads) on the integrated circuit.
When such a structure is fabricated, parasitic capacitances are produced between a capacitor C
1
formed by the expansion electrode
15
and the epitaxial layer
2
with the intervening insulation layer
16
, on the one hand, and a p-n junction capacitor C
2
formed by the epitaxial layer
2
and the substrate
1
, where both capacitances become grounded to the substrate
1
biased at the ground potential GND. The magnitude of such parasitic capacitances can reach several tens of pF so that the detrimental effects can reach a level that is not to be ignored.
FIG. 2
shows a schematic circuit diagram that includes the capacitances C
1
, C
2
. One end of the ECM is connected to the gate electrode (input terminal) of J-FET
17
, and the source electrode of the J-FET
17
is grounded, and the drain electrode is connected to the output terminal OUT. The output terminal OUT is connected to the integrated circuit comprised of n-p-n transistors. The capacitances C
1
, C
2
are connected in series between the gate electrode of the J-FET
17
and the ground potential GND. In such a circuit, output signals from the ECM flows from the ECM to the ground potential GND (shown by current i in the diagram), resulting a problem that the signal level to be impressed on the gate terminal of J-FET
17
is reduced so that desirable output voltage from the ECM cannot be obtained.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a semiconductor device, which is suitable for use to connect electric condenser microphones.
To achieve the above object, there is provided a semiconductor device, which comprises a conductivity-type substrate, an epitaxial layer formed on top of the substrate; island regions separating the epitaxial layer; an input transistor formed on one of the island regions; an insulation layer covering the surface of the input transistor layer; an expansion electrode formed above the insulation layer so as to provide an electrical connection to an input terminal of the input transistor; and resistivity of the epitaxial layer formed below the expansion electrode being in a range of 100~5,000 &OHgr;·cm.
The present semiconductor device provides an advantage that it is possible to prevent leakage of signal current from the expansion electrode by minimizing the parasistic capacitance formed between the expansion electrode and the substrate, which is at the ground potential. The parasistic capacitance is extremely reduced by increasing the specific resistivity of the epitaxial layer, up to 100~5,000 &OHgr;·cm.
Also, another advantage is that an n-p-n transistor can be fabricated by forming an n-type collector layer within the island region, in spite of the increase in the specific resistivity of the epitaxial layer.
The above and other objects, features, and advantages of the present invention will become apparent from the following description when taken in conjunction with the accompanying drawings which illustrates preferred embodiments of the present invention by way of example.
REFERENCES:
patent: 5254864 (1993-10-01), Ogawa
patent: 5273912 (1993-12-01), Hikida
patent: 5605851 (1997-02-01), Palmieri et al.
patent: 5670819 (1997-09-01), Yamaguchi
patent: 5804476 (1998-09-01), Jang
patent: 2 243 485 (1991-10-01), None
patent: 58-197885 (1983-11-01), None
patent: 58-197885 (1983-11-01), None
patent: 61-160963 (1986-07-01), None
patent: 61-242059 (1986-10-01), None
patent: 62-229869 (1987-10-01), None
Ohkoda Toshiyuki
Okawa Shigeaki
Kang Donghee
Sanyo Electric Co,. Ltd.
Thomas Tom
Wenderoth , Lind & Ponack, L.L.P.
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