Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package
Reexamination Certificate
2002-05-24
2003-07-29
Ho, Hoai (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
C257S690000, C257S693000, C257S723000, C257S730000
Reexamination Certificate
active
06600218
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device. More specifically, the present invention relates to a semiconductor device that can prevent approaching or contacting of a plurality of connecting wires connecting a semiconductor chip to external electrode terminals with each other, or the connecting wires with the semiconductor chip in the manufacture of the semiconductor device.
2. Background Art
FIG. 11
is a schematic diagram for illustrating a conventional semiconductor device,
FIG. 11A
being a top perspective view, and
FIG. 11B
being a sectional view.
In a semiconductor device
200
as shown in
FIGS. 11A and 11B
, an internal active region
4
is formed on the surface of a boarded semiconductor chip
2
, and external active regions
6
are formed around the internal active region
4
. Pads
8
, which are electrodes, are disposed further outside of the external active regions
6
, that is, on the circumferential portion of the semiconductor chip
2
.
The semiconductor chip
2
is loaded on a die pad
12
, which is a boarding portion. Gold wires
10
, which are connecting wires, connect an inner lead
14
A, which is a part of an external electrode terminal
14
formed to face to the semiconductor chip
2
, and pads
8
on the surface of the semiconductor chip
2
as loops.
In such a semiconductor device
200
, since pads are disposed on the circumferential portion, time required for designing increases. Also, since the pads must be disposed on specified locations, waste space is produced. Therefore, problems of lowered productivity and increased chip size, as well as accompanying increase in production costs have arisen.
The gold wires
10
connect the inner lead
14
A and pads
8
as loops. However, if the gold wires
10
are disposed as loops, the gold wires
10
may approach or contact the circumferential portion
2
A of the semiconductor chip
2
.
In particular, the semiconductor device
200
is molded by placing the semiconductor chip
2
, the die pad
12
, gold wires
10
, the inner leads
14
A, and the like in a prescribed die, and injecting a mold resin
16
, which is a mold resin, from the mold resin inlet provided on a corner of the die. Therefore, when the mold resin
16
flows into the die, the mold resin
16
may push down the gold wires
10
, and the gold wires
10
may contact to the circumferential portion
2
A of the semiconductor chip
2
, or may contact to each other.
SUMMARY OF THE INVENTION
As described above, a semiconductor device comprising electrodes disposed outside the external active regions, that is, the circumferential portion of the semiconductor chip has problems of increased time for designing, and increased chip size. Also, since the connecting wires connect electrodes on the semiconductor chips and external electrodes as loops, the connecting wires may contact to the circumferential portion of the semiconductor chip, especially during sealing with a resin.
In order to solve such problems, the present invention proposes a semiconductor device that does not increase time for designing or chip size, and enables the prevention of contact of connecting wires to each other, or to the circumferential portion of the semiconductor chip.
According to one aspect of the present invention, a semiconductor device comprises a semiconductor chip. The semiconductor chip has an internal active region, an external active region, and a plurality of electrodes for electrically connecting the internal active region and the external active region to outside thereof, respectively. The semiconductor device also comprises a boarding portion that carries the semiconductor chip, a plurality of external electrode terminals for electrical connection to an external device, a plurality of connecting wires each connecting the electrode of the semiconductor chip and the external electrode terminal; and a mold resin that seals the semiconductor chip, the boarding portion and the connecting wires. The electrodes are disposed around the internal active region, and the external active region is disposed outside the electrodes. Accordingly, compared with the case of disposing electrodes on the circumferential portion of the semiconductor chip, the time consumed for designing can be shortened, and the size of the semiconductor chip can be minimized.
In another aspect of the present invention, in the semiconductor device, the internal active region is disposed so as to deviate from the center of the semiconductor chip. Accordingly, connecting wires easily pushed down when the mold resin is injected, can be shortened. Therefore, electrodes can be disposed around the internal active region to prevent increase in time for designing and increase in the chip size, as well as the contact of connecting wires with each other, or the connecting wires with the circumferential end portion of the semiconductor chip.
Other and further objects, features and advantages of the invention will appear more fully from the following description.
REFERENCES:
patent: 5395035 (1995-03-01), Nakao
patent: 6087722 (2000-07-01), Lee et al.
patent: 6184585 (2001-02-01), Martinez et al.
patent: 6373140 (2002-04-01), Onodera et al.
patent: 6414386 (2002-07-01), Beaulieu et al.
patent: 2001/0020735 (2001-09-01), Chikawa et al.
Aga Fumiaki
Horibe Hiroshi
Moriga Namiki
Suzuki Yasuhito
Takaki Akira
Ho Hoai
Huynh Andy
LandOfFree
Semiconductor device does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor device will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3003616