Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – For plural devices
Reexamination Certificate
2000-01-14
2002-10-29
Potter, Roy (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
For plural devices
Reexamination Certificate
active
06472745
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a semiconductor device which comprises a plurality of semiconductor chips consolidated into one unit, each semiconductor chip having an insulation film formed on its surface so as to expose electrodes located on the surface, and a rerouting wiring pattern formed on the insulation film to be connected to the electrodes, portions of the rerouting wiring pattern being designed to be capable of being connected to an external connecting terminal.
2. Description of the Related Art
Recently, with high-density mounting and the integration of LSIs, miniaturization of semiconductor chips is advancing. In a semiconductor wafer process forming transistors and wiring lines on a semiconductor wafer, since the smaller a semiconductor chip, the larger the number of chips can be obtained from one wafer, production cost can be reduced. However, since, even though a size of semiconductor chip is reduced, a package including the chip remains a certain size, improvement of productivity has hitherto been limited.
Recently, as disclosed in Japanese Unexamined Patent Publication (Kokai) No. 10-79362 (JP-A-10-79362), a semiconductor device has been proposed which can not only be fabricated by a simplified manufacturing process which combines a wafer process with a packaging process, but can also have an external chip size approximately the same as an external package size. As shown in
FIG. 9
, the semiconductor device of this type comprises a semiconductor chip
51
having aluminum (Al) pads (Al electrodes)
53
formed on its surface, a first insulation film
52
, such as a film made of polyimide, formed so as to expose the Al pads
53
, and patterned rerouting wiring lines
54
formed on the first insulation film
52
to be connected to the Al pads
53
. The Al pads
53
, the insulation film
52
, and the rerouting wiring lines
54
are formed in a semiconductor wafer process. The first insulation film
52
, such as a film of a photosensitive polyimide, is patterned through a known photolithography process to provide openings to expose the Al pads
53
. The rerouting wiring lines
54
are formed by forming a film, such as a film of copper or aluminum, on the surface of the first insulation film
52
by a sputtering process, and etching the film to provide a desired pattern, or bonding a metal foil, such as a copper foil, to the surface of the insulation film
52
, and etching the foil to provide a desired pattern.
A second insulation film
56
is formed on the surfaces of the first insulation film
52
, and rerouting wiring lines
54
, as a protective film having openings
55
exposing a portion of the rerouting wiring line
54
. The openings
55
are formed in the second insulation film
56
by, for example, applying a photosensitive solder resist to cover the first insulation film
52
and rerouting wiring lines
54
, and exposing and developing it. A solder ball
57
, as an external connection terminal, is placed in the opening
55
, and is then reflowed to be connected to the exposed portion of the rerouting wiring line
54
. Alternatively, metal posts (not shown) to be subsequently jointed to external connection terminals are formed on the rerouting wiring lines
54
, an encapsulating resin (not shown), such as an epoxy resin, is then applied in such a manner that the top ends of the metal posts are exposed, and solder balls are placed and reflowed at the top ends of the posts to be connected thereto.
In this way, a plurality of semiconductor devices
58
are simultaneously produced on a wafer (not shown). Subsequently, the wafer is cut into respective semiconductor chips
51
, which are then subjected to functional tests to provide the semiconductor device
59
in a chip size as shown in FIG.
10
.
In the semiconductor device
59
shown in
FIG. 10
, one patterned rerouting wiring line
54
connects one Al pad
53
formed and exposed at the periphery region of the semiconductor chip
51
with one solder ball
57
formed as an external connection terminal. For example, respective patterned rerouting wiring lines
54
in the semiconductor device of
FIG. 10
are formed one by one to extend from respective address electrodes A
0
to A
6
, a ground electrode Vss, a data electrode D for data signal transmission, controlling electrodes sending and receiving various controlling signals (specifically, WE for writing signal, RAS for reading signal, CAS for selecting signal, and CS for controlling signal), and a power supplying electrode Vcc, which are all formed as Al pads
53
, to respective corresponding solder balls
57
.
In the case where a semiconductor device is produced in which a plurality of semiconductor chips
51
are consolidated into one, the number of solder balls
57
formed as external connection terminals in the area of the semiconductor device which is produced in a size approximately the same as that of the consolidated semiconductor chips
51
is increased. There has been a problem that when the number of solder balls is increased and the pitch of the balls is narrowed accordingly, the formation of the rerouting wiring lies
54
separately connecting the respective Al pads
53
and the corresponding solder balls
57
provided on each of the semiconductor chip
51
is difficult. Also, in the case where such a semiconductor device is to be mounted on a substrate, the larger the number of semiconductor chips
51
, the larger the number of lands on the mounting substrate to which the solder balls are connected. Consequently, there has also been a problem that the narrowed pitch of lands makes it difficult to form patterned wiring lines to be connected to the lands on the mounting substrate.
On the other hand, in the case where semiconductor devices having an individual semiconductor chip are to be separately mounted on a substrate, there has been a problem in production that mounting of the semiconductor devices to the substrate takes a lot of time.
SUMMARY OF THE INVENTION
To solve the above problems, the invention aims to provide a semiconductor device in which a plurality of semiconductor chips are consolidated into one, and which is provided with at least a set of rerouting wiring lines formed so as to interconnect electrodes of the respective semiconductor chips, the electrodes having a function which is common to the respective semiconductor chips, the set of rerouting wiring lines having a common external connection terminal.
In one aspect, the semiconductor device according to the invention comprises a plurality of semiconductor chips consolidated into one, each semiconductor chip having formed on its surface elements, a first insulation film formed so as to expose the electrodes, patterned rerouting wiring lines formed on the first insulation film to be connected to the electrodes, and a second insulation film formed to cover the first insulation film and the rerouting wiring lines in such a manner that a portion of the rerouting wiring line is exposed for connection with an external connection terminal, wherein the semiconductor device comprises at least a set of rerouting wiring lines formed so as to interconnect electrodes of the respective semiconductor chips, the electrodes having a function which is common to the respective semiconductor chips, the set of rerouting wiring lines having a common external connection terminal.
In this semiconductor device, a solder bump may be provided on the portion of the rerouting wiring line for the connection with an external connection terminal. Also, the first insulation film may be a film formed of a photosensitive polyimide, or formed from an anisotropically conductive sheet, and the second insulation film may be a film formed of a photosensitive solder resist.
In another aspect, the semiconductor device according to the invention comprises a plurality of semiconductor chips consolidated into one, each semiconductor chip having formed on its surface electrodes, an insulation film formed so as to expose the electrodes, patterned rerouting wiring lines form
Potter Roy
Shinko Electric Industries Co. Ltd.
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