Semiconductor device

Details Semiconductor device Semiconductor device

1997-02-04

2002-12-31

Nguyen, Cuong Quang (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

C257S750000, C257S903000

Reexamination Certificate

active

06501178

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates to a semiconductor device in which a structure for providing electrical connections among a plurality of conductive films has been improved.
2. Background Art
A structure for providing electrical connections among a plurality of conductive layers or films employed in a conventional semiconductor device will first be explained by a SRAM as an illustrative example. In general, a memory cell in the SRAM is composed of six elements in total, which include four elements of N type access transistors Q
1
and Q
2
and driver transistors Q
3
and Q
4
and two elements of P type load transistors Q
5
and Q
6
as shown in FIG.
10
. However, in this case, the memory cell increases in size, because the six elements are formed on a substrate. To cope with this situation, the size of the memory cell was reduced by using TFTs as the two P type transistors, forming the four N type elements on the substrate and forming the two P type TFT on the N type elements. As this example, a memory cell is known which has been described in, for example, a Technical Digest “International Electron Devices Meeting 1991”, p. 481-484.
FIGS. 11 through 13
show memory cell patterns of such a SRAM.
FIG. 11
shows the layout of active layers
1
a
and
1
b,
an element separation region
12
, first polysilicon films
2
a
through
2
d
and a second polysilicon film
4
all formed on a semiconductor substrate. Further, shown in
FIG. 11
are a first polycontact
3
a
for connecting the active layer
1
b
and the first polysilicon film
2
c
to each other, a first polycontact
3
b
for connecting the active layer
1
a
and the first polysilicon film
2
d
to each other and second polycontacts
5
a
and
5
b
for respectively connecting the active layers
1
a
and
1
b
to the second polysilicon film
4
.
FIG. 12
shows the layout of third polysilicon films
6
a
and
6
b
and fourth polysilicon films
8
a
and
8
b.
Further, shown in
FIG. 12
are a third polycontact
7
a
for connecting a first polysilicon film
2
c
and a third polysilicon film
6
b
to each other, a third polycontact
7
b
for connecting a first polysilicon film
2
d
and a third polysilicon film
6
a
to one another, a fourth polycontact
9
a
for connecting the third polysilicon film
6
b
and a fourth polysilicon film
8
a
to each other, and a fourth polycontact
9
b
for connecting the third polysilicon film
6
a
and the fourth polysilicon film
8
a
to each other.
FIG. 13
shows the layout of metal patterns or interconnections
11
a
and
11
b.
Further, shown in
FIG. 13
are a metal contact
10
a
for connecting an active layer
1
a
and the metal interconnection
11
a
to one another and a metal contact
10
b
for connecting an active layer
1
b
and the metal interconnection
11
b
to one another.
In these drawings, each of the first polysilicon films
2
a
through
2
d
is formed as a gate electrode of a substrate transistor. The second polysilicon film
4
is formed as a GND pattern or interconnection for each memory cell. Each of the third polysilicon films
6
a
and
6
b
is formed as a gate electrode of a TFT. Each of the fourth polysilicon films
8
a
and
8
b
is formed as a source/drain and channel layer of a TFT. Finally, each of the metal interconnections
11
a
and
11
b
is formed as a bit line.
FIG. 14
is a sectional structural view taken along line A-A′ of
FIGS. 11
to
13
. In the drawing, the same reference numerals as those shown in
FIGS. 11 through 13
respectively indicate the same elements of structure as those shown in
FIGS. 11
to
13
.
Referring also to
FIG. 14
, the memory cell includes a gate oxide film
13
a
of a bulk transistor, inter-layer insulating films
13
b,
13
c
and
13
e,
and a gate oxide film
13
d
of a TFT. Incidentally, the first polysilicon films
2
a
through
2
d
and the second polysilicon film
4
may be polysilicide composed of a combination of polysilicon and a silicide layer without being composed of a single polysilicon layer alone.
A tandem contact structure formed by connecting the first polycontact
3
b,
the third polycontact
7
b
and the fourth polycontact
9
b
among the polycontacts illustrated in
FIGS. 11
to
13
is understood as viewed from FIG.
14
.
The conventional SRAM cell formed in this way has the following problems.
(1) The many polycontacts such as the first through fourth polycontacts
3
a,
3
b,
5
a,
5
b,
7
a,
7
b,
9
a
and
9
b
are required to make contact to respective polysilicon layers. Therefore, a number of polycontact masks, frequent photoengraving and etching process for polycontacts are required, resulting in complex processes.
(2) A method of reducing the number of the polycontact masks, called shared contact structures, is known.
FIG. 15
shows a sectional structure thereof. A third polysilicon film
6
provides a polycontact simultaneously with respect to an active layer
1
and a first polysilicon film
2
for forming a gate electrode of a transistor. Thus, a first polycontact becomes unnecessary by forming a third polycontact in a shared structure, so that the number of polycontacts can be reduced by one. In each symmetrical cell of the conventional SRAM, however, the two third polycontacts are necessary within the cell because of its symmetry. Since the shared contact is connected to the two layers (active layer
1
and first polysilicon film
2
in the conventional example), it is necessary to increase the size of the shared contact as compared with that of the normal polycontact from the viewpoint of the need for reliable electrical connection of the shared contact to the respective layers. As a result, a problem arises because the cell size increases.
(3) Further, as examples of a TFT, a bottom gate type TFT in which a gate electrode is provided below a polysilicon film for forming source/drain (S/D) and channel regions, and a top gate type TFT in which a gate electrode is provided above a polysilicon film for forming source/drain (S/D) and channel regions, are known. The cells shown in
FIGS. 11 through 14
respectively use the bottom gate type TFT. In general, the top gate type TFT is superior in performance to the bottom gate type TFT. When the top gate type TFT and the shared direct contact structure are adopted, the polysilicon film for the P type source/drain (S/D) region of the TFT is brought into contact with an N type active layer. In general, the connection of an N type active layer to a P type polysilicon film is apt to form a PN junction as compared with an N type polysilicon to the P type polysilicon film. If the PN junction is formed, then a adverse effect is exerted on the operation of each cell. It was therefore difficult to combine the shared direct contact and the top gate type TFT into one. The present invention has been provided to solve the conventional problems referred to above.
SUMMARY OF THE INVENTION
According to one aspect of the present invention, a semiconductor device comprises a first conductive film formed on a semiconductor substrate, a second conductive film formed on the first conductive film with a first insulating film interposed between them, a third conductive film formed on the second conductive film with a second insulating film interposed between them. And a columnar connecting portion penetrates at least the second insulating film and the first insulating film from the third conductive film so as to reach the first conductive film and the semiconductor substrate. The second conductive film is brought into contact with the columnar connecting portion at its end surface, and the thickness of the second conductive film is less than that of the third conductive film.
According to another aspect of the present invention, a semiconductor device comprises a first conductive film formed on a semiconductor substrate, a second conductive film formed on the first conductive film with a first insulating film interposed between them, a third conductive film formed on the second conductive film with a second insulatin

Affiliated with

Also associated with

Rating

Semiconductor device does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor device will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2996571