Semiconductor device

Details Semiconductor device Semiconductor device

2001-04-12

2002-12-24

Lam, Tuan T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S099000, C327S407000, C365S233100

Reexamination Certificate

active

06498522

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a clock synchronous type semiconductor device that accepts input signals inputted from the exterior in synchronization with a clock signal.
2. Description of the Related Art
Generally, a semiconductor device such as an integrated circuit, etc., is roughly divided into a logic LSI such as a microcomputer, etc., and a memory LSI such as a DRAM (Dynamic Random Access Memory), etc. The microcomputer has been publicly known as a clock synchronous type semiconductor device. On the other hand, recently, a clock synchronous type has been developed as a synchronous DRAM in the memory LSI.
The synchronous DRAM operates an interface circuit at a high rate in synchronization with an external clock signal inputted from the exterior, and enables writing and reading of data at a high rate. For example, a synchronous DRAM, the maximum operating frequency of which is 100 MHz or more, has been developed.
FIG. 1
shows an example of configuration of an input interface unit in this type of semiconductor device. The input interface unit
1
is provided with a plurality of input signal accepting circuits
3
.
The respective input signal accepting circuits
3
accept an external clock signal CLK and an input signal Din (a) (or Din (b)). The input signal accepting units
3
output internal signals Doutz (a), Doutx (a) (or Doutz (b), Doutx (b)) to an internal circuit
5
. Also, the internal signal Doutz is an in-phase signal of the input signal Din, and the internal signal Doutx is an antiphase signal of the input signal Din.
The above-described input signal accepting circuits
3
accepts an input signal Din in synchronization with the external clock signal CLK and output the accepted signal into the internal circuit
5
as internal signals Doutz and Doutx.
FIG. 2
shows an example of acceptance timing of an input signal Din in the input interface unit
1
shown in FIG.
1
. In this example, the inputting period of the input signal Din is defined in terms of setup time and hold time with respect to rise of the external clock signal CLK.
The setup time tDS is a specification of the minimum time necessary to confirm the input signal Din prior to a rise of the external clock signal CLK, and the hold time tDH is a specification of the minimum time necessary to hold the input signal Din after a rise of the external clock signal CLK.
By inputting an input signal Din in compliance with the above-described timing specification, the input signal Din is accepted by the rise of the clock signal CLK to generate internal signals Doutz and Doutx.
The setup time tDS and hold time tDH are determined so that the input signal Din can be accepted without fail under the worst conditions, taking into consideration the characteristic fluctuations among semiconductor devices, which are produced in a semiconductor fabrication process, and temperature and/or supply voltage to operate the semiconductor devices.
However, it is necessary that users who have this type of a semiconductor device mounted in a system equipment establish an input signal Din, which is inputted into the semiconductor device, prior to the setup time tDS, and designs the timing in the system equipment to hold it longer than the hold time tDH, as described above.
The system equipment needs a circuit to satisfy the setup time tDS and a circuit to satisfy the hold time tDH, respectively, in order to generate input signals Din, so the circuit configuration of the system equipment has been increasing in scale and has been becoming more and more complicated.
In the case of a semiconductor device whose operating frequency exceeds 100 MHz, generally, the cycle of the external clock signal CLK becomes 10 ns or less. Resultantly, the allowance in the timing design at the system equipment is reduced, and it was difficult to generate input signals Din on the basis of the above-described timing specification.
In particular, in order to secure the setup time tDS of an input signal Din, a rise or a fall of an eternal clock signal CLK one clock cycle beforehand needs to be used, wherein the timing design was very difficult where the cycle of the external clock signal CLK is short.
Therefore, the inventors considered outputting an input signal Din from the system equipment as soon as the external clock signal has done transition, generating a clock signal delayed by a predetermined time with the external clock signal CLK in the above-described input interface unit
1
, and accepting an input signal Din in synchronization with the clock signal.
FIG. 3
shows a configuration of an input interface unit
1
that has been considered by the inventors. The input interface unit
1
has the above-described input signal accepting circuits
3
and an inverter
7
.
The inverter
7
inputs the external clock signal CLK, and outputs an inverted clock signal /CLK of the external clock signal CLK. The input signal accepting circuits
3
inputs the inverted clock signal /CLK. The other configuration is identical to that shown in FIG.
1
.
FIG. 4
shows timing for accepting input signals Din in the input interface unit
1
shown in FIG.
3
.
The input signal Din is accepted at a rise (=a fall of the external clock signal CLK) of the inverted clock signal /CLK. In this case, the inputting period of the input signal Din is a specification of the setup time tDS
1
and hold time tDH
1
with respect to the rise of the inverted clock signal /CLK.
Therefore, when the inputting period of the input signal Din can make the time tDS from the rise of the external clock signal CLK to the establishment of data smaller than a ½ cycle of the external clock signal CLK, only the hold time tDH with respect to the rise of the external clock signal CLK need be satisfied.
Resultantly, in the system equipment, users only has to design the timing so that an input signal Din simultaneously generates with the rise of an external clock signal CLK or after the rise thereof, and so that the rise it is held for only the hold time tDH. That is, designing of timings can be facilitated.
FIG. 5
shows the configuration of another input interface unit
1
considered by the inventors. The input interface unit
1
has the above-described input signal accepting circuits
3
and a delay circuit
9
.
The delay circuit
9
receives the external clock signal CLK, and outputs a delay clock signal DCLK delayed by a predetermined time to the external clock signal CLK. The respective input signal accepting circuits
3
receives the delay clock signal DCLK. The other configuration thereof is identical to that shown in FIG.
1
.
The delay circuit
9
is composed of, for example, a capacitor and a resistor and has a predetermined time constant.
FIG. 6
shows the accepting timing of an input signal Din in the input interface unit
1
shown in FIG.
5
.
The input signal Din is accepted at the rise of the delay clock signal DCLK delayed by delay time “Delay” from the rise of the external clock signal CLK. In this, the inputting period of the input signal Din is a specification of the setup time tDS
2
and hold time tDH
2
with respect to the rise of the delay clock signal DCLK.
Accordingly, when the time tDS from the rise of an external clock signal CLK to the decision of data can be made shorter than the delay time “Delay”, the inputting period of an input signal Din only needs to satisfy the hold time tDH of the rise of the external clock signal CLK.
Therefore, in the system equipment, users only need to design the timing so that generating input signal Din simultaneously with the rise of an external clock signal CLK or after the rise thereof as in the input interface unit
1
shown in
FIG. 3
, and hold the rise of the input signal Din for only the hold time tDH. That is, designing timings can be facilitated.
The considerations made by the inventors are not publicly known so far.
However, in the input interface unit
1
having an inverter
7
shown in
FIG. 3
, an input signal Din is accepted by using an inverted clock signal /CLK obtain

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