Active solid-state devices (e.g. – transistors – solid-state diode – Heterojunction device – Field effect transistor
Reexamination Certificate
2001-06-27
2002-10-15
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Heterojunction device
Field effect transistor
C257S194000, C257S027000, C257S020000, C257S096000
Reexamination Certificate
active
06465814
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device comprising an active layer and an electron supply layer and utilizing a two-dimensional electron gas produced in an interface between the layers.
2. Description of the Related Art
AlGaN/GaN HJFETs are considered as promising devices with high power and high withstand voltage. A conventional AlGaN/GaN HJFET has a configuration in which a plurality of gallium nitride group semiconductor layers are stacked on a substrate, for example as disclosed in U.S. Pat. No. 5,192,987 by M. A. Khan. Each semiconductor layer has uniform composition in a horizontal plane perpendicular to the thickness direction of the layers.
In semiconductor devices of this kind, one of important considerations is to simultaneously realize high withstand voltage between a gate and a drain and a higher current density in an active layer, and an electrode of low contact resistance. To this end, it is necessary to vary distribution of carriers in a channel layer and a surface layer within a plane to increase withstand voltage between a gate and drain by reducing a channel concentration in an area under the gate or between the gate and drain and to realize low contact resistance by increasing a channel concentration in source and drain areas. For this purpose, conventionally, an area in a low carrier concentration and an area in a high carrier concentration are separately formed by performing ion implantation to partially change a dose, or areas in different carrier concentrations are separately formed by stacking layers in different carrier concentrations and then recess-etching a portion of the layers. For example, in AlGaAs/GaAs, GaAs doped in high concentration is formed on a surface to form an ohmic electrode, and the heavily doped area is partially removed to form a gate electrode.
In AlGaN/GaN, however, when a heterojunction is formed on a (0001) surface, more carriers are induced with a piezo effect and a spontaneous polarization effect than with a doping concentration. Even when layers in different doping concentrations are formed and a portion thereof is removed, the effect of providing a difference in electron concentration within a plane is not produced sufficiently. The piezo effect is determined by the composition of stacked layers, and induced carriers depend on the thickness of the layer if it is smaller than a critical thickness at which dislocation occurs. Thus, while an effect can be obtained to some extent by partially removing a uniform film through recess-etching, the effect is insufficient to form a greater difference in carrier concentration. In addition, a large difference in thickness is required to obtain a large difference in concentration, which makes it difficult to achieve a reduced difference in height.
On the other hand, it is known that gallium nitride semiconductor materials typically have a low activation rate from ion implantation, and thus contact resistance tends to be high. To address such a problem, J. Burm et al. have reported a configuration in which AlGaN having uniform composition in an AlGaN/GaN HJFET is recess-etched in Solid-State Electronics Vol.41, No.2, pp247, 1997. This configuration provides a small reduction in contact resistance and achieves a tolerable effect, although it is difficult to obtain a currently desired level of low contact resistance. While a configuration including a heavily doped GaAs cap layer formed on a surface of AlGaAs is employed in the GaAs group, this results in an increase in contact resistance conversely due to piezo charge in the AlGaN/GaN group.
SUMMARY OF THE INVENTION
The present invention has been made in view of the aforementioned circumstances, and it is an object of the present invention to produce a distribution of two-dimensional electrons serving as carriers in a horizontal plane perpendicular to a thickness direction of layers to form a desired device configuration. Specifically, when the present invention is applied to a transistor configuration, the present invention intends to improve withstand voltage between a gate and a drain by reducing a channel concentration under the gate and to realize low contact resistance by increasing a channel concentration in source and drain areas. When the present invention is applied to a monolithic microwave integrated circuit, the present invention intends to form a higher resistance element and a lower resistance element separately with simple steps and good controllability.
According to the present invention, provided is a semiconductor device comprising an active layer, and an electron supply layer in which induced charge including piezo charge is produced, the active layer and the electron supply layer being stacked in this order and having an interface between them at which a two-dimensional electron gas is formed, wherein the induced charge has a distribution within a horizontal plane perpendicular to the thickness direction of the layers and a distribution of two-dimensional electron concentrations is formed within the horizontal plane in accordance with the distribution of the induced charge.
With the semiconductor device, since the distribution of two-dimensional electron concentrations is formed in accordance with the distribution of the induced charge including piezo charge within the horizontal plane, it is possible to form an area of high channel resistance and an area of low channel resistance with good controllability. The induced charge includes both charge due to piezo polarization and charge due to spontaneous polarization. To produce such induced charge significantly, both active layer and electron supply layer are preferably formed of a group III nitride semiconductor. A crystal growth surface in this case is preferably a (0001) surface. It should be noted that, in this specification, the (0001) surface in group III nitride semiconductor crystal refers to a hatched surface in an arrangement shown in FIG.
3
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The semiconductor device may be configured such that a first area having a relatively low two-dimensional electron concentration is formed under a gate electrode and a second area having a relatively high two-dimensional electron concentration is formed under a source electrode, under a drain electrode, between the gate electrode and the drain electrode, or between the gate electrode and the source electrode. When such a configuration is used, a channel concentration under a gate is reduced to improve withstand voltage between the gate and a drain, while a channel concentration in source and drain areas is increased to realize low contact resistance. The first area may be formed in at least a portion of a region under the gate electrode, and the second area may be formed in at least a portion of the aforementioned regions. For example, the second area may be formed only in a portion of a region under the source electrode. It is preferable, however, that the second area is provided for each of the source and drain sides to allow a reduction in both source electrode resistance and drain electrode resistance. As an example of preferred arrangements of the first and second areas, the first area is formed under the gate electrode and in an area closer to the gate electrode between the gate and drain, and the second area is formed in an area where the first area is not formed between the source and drain and under each of the source and drain electrodes.
The semiconductor device may be configured such that the area having a relatively low two-dimensional electron concentration is used as a higher resistance element, and the area having a relatively high two-dimensional electron concentration is used as a lower resistance element. When such a configuration is used, the higher resistance element and lower resistance element can be formed separately with simple steps and good controllability. In the present invention, “a relatively low two-dimensional electron concentration” refers to a two-dimensional electron concentration lower than a two-dimensional electr
Ando Yuji
Hayama Nobuyuki
Kasahara Kensuke
Kunihiro Kazuaki
Kuzuhara Masaaki
Huynh Andy
McGinn & Gibb PLLC
NEC Corporation
Nelms David
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