Semiconductor device

Active solid-state devices (e.g. – transistors – solid-state diode – Regenerative type switching device – Combined with field effect transistor

Reexamination Certificate

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Details

C257S339000, C257S342000, C257S653000

Reexamination Certificate

active

06459101

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to a high voltage semiconductor device, and more particularly to a high voltage lateral power semiconductor device for a switching power supply, a motor drive, a fluorescent inverter drive and the like.
BACKGROUND OF THE INVENTION
PWM control method has become widespread for a switching power supply, a motor drive and a fluorescent inverter drive. With respect to a control circuit, there is the need for improving the function, reducing the size and cost, improving the reliability and reducing the electricity consumption. Accordingly, there is an increasing demand for a power IC in which high voltage power elements are integrated. A power IC for a power supply, which drives commercial 100-200V, requires an element breakdown voltage of 700V in order to drive a transformer. To facilitate the integration with a control part, the power IC must be lateral and its substrate and drift region has a high resistivity (a low impurity concentration) (Journal of Electricity EDD-93-21, P21-29, Toshihiko Uno et al. “Reduction in ON resistance of a high voltage lateral power MOSFET for IPD”). With respect to the layout of the device, opposite electrodes must be arranged in the teeth of comb pattern in order to improve a current driving performance per unit area. To improve the integration degree, however, the radius of curvature is small at a corner part of the teeth of comb pattern. This induces the local concentration of electric fields, and lowers the breakdown voltage by about 20%.
FIG. 18
is a plan view of a conventional high voltage lateral power semiconductor device as a first example, and
FIG. 19
is a cross-sectional view taken along line A-B of FIG.
18
. As shown in
FIG. 19
, this semiconductor device is constructed in such a manner that an N well
2
and a P base
3
are formed on a p type substrate with a high resistivity of about 150 &OHgr;cm. The N well
2
has a surface impurity concentration of 1×10
16
/cm
3
, and a diffusion depth of 6 &mgr;m. The amount of donor in the N well
2
is 1×10
12
/cm
2
. The total amount of donor in the N well, the resistivity of the P substrate and the distance of the drift region are optimized to achieve a high breakdown voltage.
The P base, which forms a source region, has a surface concentration of 3×10
16
/cm
3
, and a diffusion depth of 6 &mgr;m. A threshold voltage of a power MOS is determined according to the surface concentration. Then, a thermal oxide film
4
with a thickness of 0.6 &mgr;m, and a polysilicon gate
6
is formed through a gate oxide film
5
of 25 &mgr;m. An n
+
diffused layer with a surface concentration of 1×10
20
/cm
3
, and a diffusion depth of 0.2 &mgr;m is formed in a source
7
and a drain
8
, and a contact P
+
diffused layer (with a surface concentration of 5×10
19
/cm
3
, and a diffusion depth of 0.5 &mgr;m)
9
is formed on the surface of the P base. An interlayer insulating film
10
is formed and a contact hole
11
is opened, and then a source electrode
12
and a drain (gate) electrode
13
are formed.
In this prior art, the device is shaped like the teeth of comb having a straight portion
20
in which the P base region
3
forming the source region and the drain
8
are parallel to one another if they are viewed prospectively, and corner parts
21
,
22
having the same interval between the P base region
2
and the drain
8
as the parallel interval of the straight portion
20
. If there is the need for an actual output current capacity of 2-5A class, a channel width must be not less than 50 mm and the number of teeth of comb must be more than 10 and less than 20.
In this prior art, the straight portion
20
and an end portion of the teeth of comb pattern at the corner part have the cross-sectional structure shown in FIG.
19
. If the radius of curvature is 100 &mgr;m, the breakdown voltage is 800V. If, however, radius of curvature is 12.5 &mgr;m, the electric fields are heavily concentrated at the corner part. This lowers the breakdown voltage to 600V. Therefore, the radius of curvature must be not less than 50 &mgr;m in order to ensure the breakdown voltage of 700V. More specifically, a device pitch cannot be reduced, and it is therefore impossible to improve the current driving performance per unit area. Accordingly, the breakdown voltage of the power semiconductor device is 700V and the ON resistance per unit area is about 90 &OHgr;/mm
2
in this prior art.
FIG. 20
is a cross-sectional view of a conventional high voltage lateral power semiconductor device as a second example. A plan view thereof is the same as FIG.
18
.
In the second example, an N well
2
A is formed on a p type substrate
1
with a high resistivity of about 150 &OHgr;cm, and a P base
3
A is formed inside the N well
2
A. The N well
2
A has a surface impurity concentration of 1×10
16
/cm
3
, and a diffusion depth of 6 &mgr;m. The amount of donor in the N well
2
A is 1×10
12
/cm
2
. The total amount of donor in the N well
2
A, the resistivity of the P substrate
1
and the distance of the drift region are optimized to achieve a high breakdown voltage. The P base
3
A has a surface concentration of 3×10
16
/cm
3
, and a diffusion depth of 2 &mgr;m. A threshold voltage of a power MOS is determined according to the surface concentration. A p type surface region
14
is formed between the P base
3
A and an n
+
drain. The p type surface region
14
has a surface impurity concentration of 5×10
16
/cm
3
, and a diffusion depth of 1 &mgr;m.
In the prior art of the second example, a straight portion and a corner part
22
A (see
FIG. 18
) at an end portion of the teeth of comb have the cross-sectional structure shown in FIG.
20
. If the radius of curvature is 100 &mgr;m, the breakdown voltage is 800V. If, however, radius of curvature is 12.5 &mgr;m, the electric fields are heavily concentrated at the corner part. This lowers the breakdown voltage to 600V. For this reason, the radius of curvature cannot be reduced to not less than 50 &mgr;m in order to ensure the breakdown voltage of 700V. More specifically, the device pitch cannot be reduced, and it is therefore impossible to improve the current driving performance per unit area. Accordingly, the ON resistance per unit area is as high as 60 &OHgr;/mm
2
if the radius of curvature is set at 50 &mgr;m in order to ensure the breakdown voltage of 700V.
To address this problem, a semiconductor device of the third example is known in which a drain corner part has an electric field reliving structure as disclosed in Japanese Patent Provisional Publication No. 6-244412.
FIG. 21
is a plan view showing a prior art of the third example, and FIGS.
22
(
a
)-
22
(
c
) are partial cross-sectional views showing principal parts of FIG.
21
. FIG.
22
(
a
) is a cross-sectional view taken along line A-B of
FIG. 21
, FIG.
22
(
b
) is a cross-sectional view taken along line C-D of
FIG. 21
, and FIG.
22
(
c
) is a cross-sectional view taken along line E-F of FIG.
21
. In this structure, the end portion
22
A at the drain corner part in
FIG. 18
is shortened as shown in
FIG. 21
, and the p type surface region
14
in this region is eliminated by a length L and a width W to form an n type surface region
16
. The width W of the eliminated region is optimized to thereby relieve the electric fields at the corner part.
In this structure, however, the relief of the electric fields must be adjusted within the width of the p type surface region
14
in the N well
2
A of at the drain corner end portion. Since the N well
2
A has a relatively high surface impurity concentration, the range of optimum values of the width W is very narrow and this increases the dispersion in the breakdown voltage. For this reason, the radius of curvature needs to be 30 &mgr;m in order to ensure the breakdown voltage of 700V, and thus, the ON resistance per unit area is lowered by only 15%. It is therefore impossible to satisfactorily lower the ON resistance.
As stated above, the convention

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