Active solid-state devices (e.g. – transistors – solid-state diode – Regenerative type switching device – Combined with field effect transistor
Reexamination Certificate
2000-05-09
2002-10-29
Flynn, Nathan J. (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Regenerative type switching device
Combined with field effect transistor
C257S137000, C257S131000
Reexamination Certificate
active
06472692
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a semiconductor device with four-layer structure (PNPN structure) such as thyristor.
BACKGROUND ART
Semiconductor devices for a large amount of electric power have been improved to deal with a high pressure and a large amount of current. A gate commutation thyristor element (hereinafter referred to as GCT element), for example, allows now a maximum current of 4000A driven by DC3000V to flow without any snubber circuit.
FIG. 6
is a diagram showing a basic circuit applicable to a GCT element in the case that a snubber circuit is added.
FIG. 7
is a diagram showing a basic circuit applicable to a GCT element in the case that any snubber circuit is not added. In
FIG. 6
, reference numeral
101
is a GCT element that is connected in series to a power source and to a circuit where a load and a free wheel diode are connected in parallel. Numeral
102
is a snubber circuit, comprising a capacitor, a diode and a resistor, which is connected between the anode and the cathode of the GCT element
101
. In
FIG. 7
, numeral
103
is a voltage clamping circuit, comprising a diode and a capacitor, which is connected between the anode and the cathode of the GCT element
101
. Numeral
104
is a resistor connected between the power source and a terminal located between the diode and the capacitor in the voltage clamping circuit
103
. The remaining elements in
FIG. 7
are the same as
FIG. 6
, except the snubber circuit
102
. Therefore, a further description is omitted herein.
As shown in
FIG. 6
, in a turn-off operation where the snubber circuit
102
is added, after starting the turn-off operation, the GCT element
101
begins to restore its voltage blocking characteristic, and begins to block the voltage. Simultaneously, a current begins to flow in the snubber circuit
102
that is connected in parallel with the GCT element
101
. In this manner, it is possible to cause the current that has been flowing in the GCT element
101
to flow in the snubber circuit
102
and to reduce the current in the GCT element
101
. As a result, a turn-off operation with a small amount of turn-off loss can be performed.
On the other hand, in a turn-off operation shown in
FIG. 7
where the snubber circuit
102
is not added, after staring the turn-off operation, the GCT element
101
begins to restore its voltage blocking characteristic, and begins to block the voltage. Then, the element voltage reaches a source voltage, and upon reaching the source voltage, the current flowing in the GCT element
101
begins to reduce. This means that the current continues to flow in the element until the element voltage reaches the source voltage, and turn-off loss of the GCT element itself increases by several tens of percent or more as compared with the case where the snubber circuit
102
is added.
To cope with this disadvantage, a GCT element has been proposed, in which turn-off loss is reduced without adding any snubber circuit, element voltage of the GCT element quickly reaches source voltage, and current can be quickly reduced.
FIG. 8
is a sectional view showing a conventional GCT element.
FIG. 9
is a top view showing the conventional GCT element viewed from a cathode side.
FIG. 8
shows a section taken along the line A—A in FIG.
9
. In
FIG. 8
, numeral
111
is an N
−
region made of an N
−
semiconductor substrate containing impurities of a lower-concentration. The N
−
region
111
is comprised of two layers; one is a first layer
111
a
formed to be short in lifetime due to lattice defect therein, and the other is a second layer
111
b
formed to be locally close to an N region
112
in the N
−
region
111
and to be shorter in lifetime than the first layer
111
a.
Numeral
112
is the N region made of an N-type semiconductor formed on the face of the second layer
111
b
side in the N
−
region
111
. Numeral
113
is a circular-shaped or torus-shape P emitter region made of a P-type semiconductor, formed selectively on top of the N region
112
. Numeral
114
is a P base region made of a P-type semiconductor formed on the face of the first layer
111
a
side in the N
−
region
111
. Numeral
115
is N emitter region made of an N-type semiconductor, formed selectively on top of the P base region
114
.
Numeral
116
is a cathode electrode made of a metal such as aluminum, formed on top of the N emitter region
115
. Numeral
117
is a gate electrode formed on top of such areas of the P base region
114
where the N emitter region
115
is not formed. Numeral
118
is an anode electrode formed on top of the P emitter region
113
and also on top of the N region
112
that are estranged by the P emitter region
113
. The P emitter region
113
and the N region
112
are short-circuited at the anode electrode
118
and form an anode short-circuit structure.
A top view from a cathode side of the element is shown in FIG.
9
. The gate electrode
117
is formed on top of the P base region
114
. In a radial pattern from the center of the gate electrode
117
, four elliptical regions are formed selectively in the areas where the electrode
117
is not formed. In each of the elliptical regions, the N emitter region
115
is formed so as not to be in contact with the gate electrode
117
, and the elliptical cathode electrode
116
is formed on top of the N emitter region
115
.
FIG. 10
shows a distribution of lifetimes of the semiconductors in the N
−
region
111
shown in
FIGS. 8 and 9
. As shown in
FIG. 10
, in order to form the layers that have different lifetimes from each other, first, lattice defects are evenly formed in the N
−
region
111
by electron beam irradiation technique to shorten the lifetime. Then, comparatively heavy ions such as proton are implanted into the second layer
111
b
to produce a regional crystal imperfection in the area making consequently the lifetime of the second layer
111
b
shorter than that of the first layer
111
a
(i.e., the N
−
region
111
excluding the second layer
111
b
). In this manner, by forming the lattice defects therein, the lifetime of the first layer
111
a
in the N
−
region
111
is controlled to be within a range of 50 to 200 &mgr;s and that of the second layer
111
b
is controlled to be within a range of 1 to 100 &mgr;s, respectively.
Operation of the above mentioned conventional semiconductor device is hereinafter described.
The semiconductor device indicated in both FIG.
8
and
FIG. 9
is arranged to be connected to the circuit without any snubber circuit, as shown in FIG.
7
. When the turn-off operation is made under this condition, a depletion layer starts to be formed in a direction from the PN junction between the P base region
114
and the N
−
region
111
toward the anode side. Since the lifetime of the first layer
111
a
of the N
−
region
111
is formed shorter, the depletion layer is quickly formed in the area near the PN junction between the P base region
114
and the N
−
region
111
. Then, this depletion layer extends to the anode side and reaches the second layer
111
b
in the N
−
region
111
. At this point, since the lifetime of the second layer
111
b
is formed shorter than that of the first layer
111
a
, extension speed of the depletion layer is further accelerated in the second layer
111
b
. That is, residual carriers are quickly vanished. As a result, a tail electric current caused by the residual carriers can be reduced.
FIG. 11
shows a main electric current and a main electric voltage at a turn-off operation of the conventional semiconductor device. As shown in
FIG. 11
, with the decrease of the main current at the turn-off operation, extension speed of a depletion layer increases, and current dropping speed is increased. Consequently, with the increase of current dropping speed, a very high spike voltage is generated.
In order to further improve formation speed of a depletion layer at the initial stage of turn-off operation, a further semiconductor device is disclose
Koga Shinji
Morishita Kazuhiro
Satoh Katsumi
Flynn Nathan J.
Mondt Johannes
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