Active solid-state devices (e.g. – transistors – solid-state diode – Dram configuration with transistors and capacitors of pairs...
Reexamination Certificate
2000-04-20
2002-06-18
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Dram configuration with transistors and capacitors of pairs...
C438S238000
Reexamination Certificate
active
06407464
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing a semiconductor device. More particularly, the invention relates to a semiconductor device in which a short-circuit between gate interconnections and bit lines caused by a dummy pad contact formed at an end of memory cells using a self-alignment method is avoided, and to a method of manufacturing a semiconductor device in which a step produced between memory cells and their peripheral portions can be eliminated by forming and polishing a dummy pad contact at the end of memory cells.
2. Description of the Background Art
In recent years, the degree of integration of semiconductor devices has been enhanced and memory cells have been reduced in size, so that it has been difficult to form contacts in the gap between interconnections only by photo-resist masking without short-circuiting the interconnections. One of the methods used for forming contacts in gaps of interconnections without short-circuiting is a so-called self-alignment method.
FIG. 28
shows a sectional view of a pad contact hole opened in an interlayer oxide film using this self-alignment method. In
FIG. 28
, a silicon interconnection
902
which comes to be a gate interconnection is formed on a semiconductor substrate
910
with an insulating film
901
interposed, and is coated with nitride layers
903
,
904
. On an interlayer oxide film
905
deposited on these layers, a pad contact hole
915
, where a pad contact is formed for conducting an active region
911
and a top layer portion, is opened.
The self-alignment method in general is now described in order. First, a silicon interconnection is deposited on a semiconductor substrate with an insulating film interposed. A nitride film protecting the silicon interconnection is then formed on the top and the side surfaces of the silicon interconnection. In this step, the silicon interconnection comes to be coated with the nitride film. Thereafter, an interlayer oxide film is deposited and then the interlayer oxide film is etched to open a contact hole using a photoresist mask on a desired position. When the interlayer oxide film is etched with selective ratio of the oxide film (i.e., the interlayer oxide film) to the nitride film being greater than prescribed value, the silicon interconnection can be protected from etching, by the nitride film on the top and the side surfaces. Thus, if the opening diameter of pad contact hole
915
is larger than the interval between silicon interconnections, as shown in
FIG. 28
, the opening diameter would be overlapped with the silicon interconnections. No short-circuit occurs, however, as the silicon interconnection is protected by the nitride layer. Therefore, as shown in the sectional view of
FIG. 29
, the nitride films
903
,
904
on the top and the side surfaces of the silicon interconnections are left with a sufficient thickness, even when the pad contact hole
915
is opened. With this method, the pad contact can be formed without short-circuiting the silicon interconnection and the pad contact.
On the other hand, from the reason described in the following, at end portions of memory cells, a dummy pattern such as a dummy pad contact is generally provided. Since the continuity (repetition) of the pattern is lost at the end of the memory cells, the pattern at the end-most portion, especially the contact diameter, is reduced due to an optical proximity effect. To dissolve this inconvenience, a dummy contact is provided around a body of the memory cells. By providing the dummy contact, though the dummy contact diameter becomes small due to an optical proximity effect, the memory cell body contact formed inner than the dummy contact can have an intended size. In this case, it is very difficult to control the size of the pattern in the end-most portion. For example, even when the size of the mask is set a little larger than that of the pad contact in the memory cell, the diameter of pad contact
921
at the end may possibly be oversized, resulting in short-circuiting with adjacent pad contact
920
positioned inside. In
FIG. 30
, there is also shown an arrangement of a gate interconnection
930
and another pad contact (the second pad contact)
906
on which a bit line contact is formed. In the following description, pad contact
906
formed overlapped with the bit line when viewed two-dimensionally will be referred to the second pad contact, and is distinguished from pad contact
921
(the first pad contact) formed between the bit lines. Furthermore, in particular, when referred simply as “contact” or “pad contact”, it will include both pad contacts.
Thus, as it is difficult to control the size of the pad contact at the endmost portion, as shown in
FIG. 31
, a mask opening
924
of the first pad contact in the dummy and a mask opening
925
of the first pad contact of the memory cell body are normally formed to have the same size. In
FIG. 31
, there is also shown a mask opening
926
for the second pad contact
906
. As a result of setting mask opening
924
of the first pad contact in the dummy, the diameter of first pad contact
921
of the dummy becomes smaller than that of first pad contact
920
of the cell body, as shown in FIG.
32
.
The above-described self-alignment method has the following problems. When a contact hole is opened using the self-alignment method and the hole diameter of the photo-resist to be an etching mask is small, the tip portion of the etching gas opening the interlayer oxide film will not contact in wide area with the nitride film on the top and side of the interconnection. When the etching gas contacts in wide area with the nitride film coating the interconnection, the etching selective ratio of the oxide film (i.e., the interlayer oxide film) to the nitride film is high in etching so that the etching gas will not much etch the nitride film. The reason for this is as follows: C
4
F
8
, C
5
F
8
, CH
2
F
2
and so forth are used as etching gas species, and these plasma gas etch the interlayer oxide film and the nitride film while depositing a film of polymer including C on the nitride film. Thus, when the contact area between the nitride film of the gate interconnection coating and the etching gas is wide, the nitride film is etched while the sufficient deposition film being deposited. When only a corner of the gate interconnection coating and the etching gas contacts, however, the deposition does not much proceed while the etching only proceeds. Therefore, when the diameter of the contact hole is small, the etching selective ratio of the oxide film to the nitride film in the etching will be low. At the end portion of the memory body, the diameter of the contact hole becomes smaller due to an optical proximity effect, so that the etching selective ratio of the oxide film to the nitride film on the etching will be low. Thus, if the dummy pad contact is formed at the end of the memory cells using the self-alignment system, the remaining nitride film will be thinner as shown in the circle A in FIG.
33
. Therefore, at the step in which the nitride film at the contact bottom is eliminated, the interconnections are exposed at the top and the side wall of the interconnections, as shown in the circle B in FIG.
34
. As a result, filling a plug to form a pad contact causes short-circuit with the pad contact.
Today, as the sizes of semiconductor devices and contacts thereof are more and more being reduced, the frequency of such short-circuits tends to be increasing. In the case of a contact in a memory cell body, a mask opening may be so provided as to enable the etching gas to somehow contact in a wide area with the nitride film on top and side wall portions of the interconnections. With respect to a dummy pad contact which is smaller in size due to an optical proximity effect, however, the contact area with the nitride film is smaller so that the nitride film is, in fact, easily eliminated by etching. Thus, when a pad contact is formed between gate interconnect
Le Bau T
McDermott & Will & Emery
Mitsubishi Denki & Kabushiki Kaisha
Nelms David
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