Semiconductor device

Details Semiconductor device Semiconductor device

2001-08-13

2002-10-29

Zweizig, Jeffrey (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific identifiable device, circuit, or system

With specific source of supply or bias voltage

Reexamination Certificate

active

06472929

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device comprising an input circuit which operates in accordance with a reference potential, and more particularly, to countermeasures to noise introduced into a reference potential supplied to a plurality of input circuits.
Latest semiconductor memory devices receive power from various external power supplies due to the tendency toward an increased number of bits and larger scale of die size. For example, a driver circuit for I/O pads is supplied with power from external dedicated power supplies VccQ, VssQ, while general peripheral function circuits within a device are supplied with power from external general power supplies Vcc, Vss. Among the peripheral function circuits, a circuit for converting the level of a small voltage supplied from an external input pin, and a sense amplifier for discriminating a small potential difference are vulnerable to external noise, so that they are separated from circuits which consume a large amount of power, such as a delay locked loop (DLL) circuit. In this event, wires associated with the power supplies Vcc, Vss for the sense amplifier are separated from pads for the DLL circuit.
FIG. 1
is a schematic circuit diagram illustrating a sense amplifier
100
of a semiconductor integrated circuit which is described in Japanese Unexamined Patent Publication No. 2000-11649. The sense amplifier
100
is supplied with an internal supply voltage Vint to a node N
1
via a low pass filter
1
. The node N
1
is connected to an inverter circuit
2
, so that a voltage changing rate at the node N
1
is adjusted in response to a changing rate of a reference voltage Vref supplied to the inverter circuit
2
.
When the internal supply voltage Vint rises, potentials at nodes N
2
, N
3
once rise, and a potential difference is generated between the nodes N
2
and N
3
based on the internal supply voltage Vint. A latch circuit
3
performs a latch operation in accordance with the potential difference. This configuration prevents the latch operation from starting with unstable voltage levels at the nodes N
2
, N
3
, so that a normal latch signal is output from the latch circuit
3
.
After the internal supply voltage Vint has risen, the internal supply voltage Vint may be supplied to other circuits. In this event, a consumed current temporarily increases to cause sudden fluctuations in the level of the internal supply voltage Vint. However, high frequency noise caused by the fluctuations in the internal supply voltage Vint is removed by the low pass filter
1
. Therefore, the latch circuit
3
is prevented from erroneous operations due to fluctuations in the internal supply voltage Vint.
In the sense amplifier
100
, the internal supply voltage Vint is supplied to the inverter circuit
2
via the low pass filter
1
, while the reference voltage Vref is supplied to the inverter circuit
2
without intervention of a low pass filter. In this event, for avoiding the influence of noise in the reference voltage Vref, it is necessary to commonly provide a power supply Vss of a voltage generator circuit for generating the internal supply voltage Vint, a power supply Vss of a reference voltage generator circuit for generating the reference voltage Vref, and a power supply Vss of the sense amplifier. This requirement imposes a large constraint on designing of layouts of the respective generator circuits, sense amplifier and power supply wiring, and results in a larger die size of the device.
FIGS. 2 through 5
are schematic circuit diagrams illustrating an internal power supply circuit
200
for a semiconductor integrated circuit described in Japanese Unexamined Patent Publication No. 2000-124797.
The internal power supply circuit
200
includes a boost power generator circuit
4
, two control voltage generator circuits
5
a
,
5
b
, and four power supply circuits
6
a
to
6
d.
The boost power generator circuit
4
receives power from a power supply Vcc
2
and a power supply Vss
2
, and performs a pumping operation in accordance with an oscillating signal supplied from an oscillator
7
and having a predetermined frequency to generate a boosted voltage Vpp
1
. The boosted voltage Vpp
1
is supplied to the first and second control voltage generator circuits
5
a
,
5
b
which have the same configuration.
The first control voltage generator circuit
5
a
generates a first control voltage Vg
1
which is higher than the reference voltage Vref by a predetermined voltage based on the boosted voltage Vpp
1
and the power supply Vss
1
. The second control voltage generator circuit
5
b
generates a second control voltage Vg
2
which is higher than the reference voltage Vref by a predetermined voltage based on the boosted voltage Vpp
1
and the power supply Vss
2
.
The first control voltage Vg
1
is supplied to the power supply circuit
6
b
for a DLL circuit (see FIG.
3
). The power supply circuit
6
b
for a DLL circuit receives power from a power supply Vcc
1
and the power supply Vss
1
, and generates a predetermined first internal supply voltage ViiD in accordance with the first control voltage Vg
1
.
The second control voltage Vg
2
is supplied to the power supply circuit
6
a
or to the power supply circuit
6
d
illustrated in FIG.
5
. Each of the power supply circuits
6
a
,
6
d
receives power from the power supply Vcc
2
and the power supply Vss
2
, and generates a second predetermined internal supply voltage ViiS in accordance with the second control voltage Vg
2
.
The power supply circuit
6
c
illustrated in
FIG. 4
generates a supply voltage Viin for other circuits in the DLL circuit. The power supply circuit
6
c
receives power from the power supplies Vcc
1
, Vss
1
or from the power supplies Vcc
2
, Vss
2
, and generates the supply voltage Viin in accordance with the first or second control voltage Vg
1
, Vg
2
.
Each of the power supply circuits
6
b
to
6
d
has a low pass filter
8
which absorbs noise introduced into each of the control voltages Vg
1
, Vg
2
.
The internal power supply circuit
200
requires a plurality of control voltage generator circuits
5
a
,
5
b
for supplying corresponding control voltages to the plurality of power supply circuits
6
a
,
6
b
,
6
c
,
6
d
connected to different power supplies. Therefore, a device which requires multiple power supplies for its operations must have multiple control voltage generator circuits laid out therein, thereby causing an increase in the die size of the device.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a semiconductor device which is capable of shutting off the influence of noise introduced into a reference voltage while preventing an increase in die size.
In one aspect of the present invention, there is provided a semiconductor device including a reference potential generator circuit for generating a reference potential in accordance with a first power supply, a first filter connected to the reference potential generator circuit and the first power supply for filtering the reference potential to generate a first filtered reference potential, a second filter connected to the reference potential generator circuit and a second power supply for filtering the reference potential to generate a second filtered reference potential, a first input circuit connected to the first filter and the first power supply for receiving the first filtered reference potential to generate a first predetermined voltage, and a second input circuit connected to the second filter and the second power supply for receiving the second filtered reference potential to generate a second predetermined voltage.
Other aspects and advantages of the invention will become apparent from the following description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the invention.


REFERENCES:
patent: 6052012 (2000-04-01), Camerlo
patent: 6157251 (2000-12-01), Camerlo
patent: A-2000-011649 (2000-01-01), None
patent: A-2000-124797 (2000-04-01), None

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