Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Amplitude control
Reexamination Certificate
2002-03-19
2002-10-29
Lam, Tuan T. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Amplitude control
C327S319000, C327S320000, C361S091500
Reexamination Certificate
active
06472923
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor device provided with an electrostatic discharge (ESD) protection circuit for protecting internal elements of the semiconductor device from destruction caused by electrostatic current and the like.
2. Description of the Related Art
Conventionally, various kinds of methods are proposed to protect semiconductor device from destruction caused by the electrostatic current and the like. However, as for protection of a signal terminal for inputting/outputting a high-speed signal or a high-frequency signal, in many cases, a relation between increase of terminal capacitance by a protection circuit or a protection element and protection performance thereof becomes a relation of “trade-off”. For that reason, compatibility of control of increase of capacity and improvement of protection performance is difficult.
For instance, the official gazette of the Japanese Patent No. 2,715,593 discloses a semiconductor integrated circuit in which protection performance is improved while controlling increase of terminal capacitance of a terminal to be protected (a first prior art).
FIG. 1A
is a circuit diagram illustrating a constitution of a semiconductor integrated circuit according to the first prior art.
In the semiconductor integrated circuit
70
according to the first prior art, a first diode
71
is connected to a high potential side power supply terminal V
CC
and an I/O terminal IN/OUT therebetween. A second diode
72
is connected to the I/O terminal IN/OUT and a low potential side power supply terminal V
EE
therebetween. A third diode
73
is connected to the high potential side power supply terminal V
CC
and the low potential side power supply terminal V
EE
therebetween. An internal circuitry
77
is connected to the I/O terminal IN/OUT, Electricity from the high potential side power supply terminal V
CC
and electricity from the low potential side power supply terminal V
EE
are supplied to the internal circuitry
77
. The respective diodes are constituted so that backward bias is applied to the respective diodes at the time the circuit is operated, and the respective diodes possess function of avalanche breakdown voltage more than voltage value that is capable of being applied. Consequently, each diode functions as an additional capacitance at the time that the circuit is operated,
FIG. 1B
is a circuit diagram illustrating operations of the semiconductor integrated circuit according to the first prior art.
For instance, as illustrated in
FIG. 1B
, there are three kinds of current paths when electrostatic discharge occurs from the high potential side power supply terminal V
CC
to the I/O terminal IN/OUT. A first path A is one in which discharge occurs through the diode
71
. A second path B is one in which discharge occurs through the internal circuitry
77
. A third path C is one in which discharge occurs through the diode
72
and the diode
73
. Accordingly, the avalanche breakdown voltage of the diode
73
is at the most of the same degree of that of the diodes
71
and
72
, and if impedance of the diode
73
is low, surge by ESD is distributed into approximately half-and-half onto the path A and the path C. For that reason, even though sizes of the diode
71
and the diode
72
are halved, resist quantity of electrostatic surge can be ensured. Conseqently, capacitive load of I/O terminal is reduced.
“ESD Protection Using a Variable Voltage Supply Clamp” (written by Gregg D. Croft (EOS/ESD Symposium Proceedings pp135-140, 1994)) discloses an integrated circuit (a second prior art) provided with a clamp device (Supply Clamp) between a positive power supply (V+) terminal and a negative power supply (V−) terminal.
According to the second prior art, even though the surge by ESD is applied to the I/O terminal, a protection diode of the I/O terminal does not cause an avalanche breakdown. Consequently, the protection diode is miniaturized with ESD event resist quantity ensured.
FIG. 2
is a block diagram illustrating a constitution of an ESD protection circuit of the integrated circuit (IC)
80
according to the second prior art.
Protection diodes D
1
and D
3
are connected to the I/O terminals
82
,
83
of IC
80
and the V
1
+ terminal therebetween, in which respective anodes of the diodes D
1
and D
3
are directed to the I/O terminal side. Protection diodes D
2
and D
4
are connected to the I/O terminals
82
,
83
and the V
1
− terminal therebetween, in which respective cathodes of the diodes D
2
and D
4
are directed to the I/O terminal side. A clamp device
85
, which is made up of a thyristor, is provided between the V
1
+ terminal and V
1
− terminal.
The protection diodes D
1
to D
4
are capable of being discharged without causing avalanche breakdown even though the surge by ESD is applied to the I/O terminals
82
,
83
in such a way that clamp voltage of the clamp device
85
is maintained to be minimized less than a value that is obtained by subtracting voltage value corresponding to voltage drop of two forward bias diodes from the avalanche breakdown voltage of the protection diodes D
1
to D
4
.
Concretely, for instance, in cases where positive surge pulse by ESD is applied to the I/O terminal
82
against the V
1
− terminal, current flows from the protection diode D
1
(forward direction) toward the V
1
+ terminal, the current flows from the V
1
+ terminal toward the clamp device
85
, and the current flows from the clamp device
85
toward the V
1
− terminal. Thus, the surge by ESD is discharged. Current does not flow toward the protection diode D
2
. Since the protection diode D
1
is operated in the forward direction, power consumption is small. Consequently, also since heat generation is small, it is possible to sufficiently miniaturize the protection diode D
1
. As to the other diodes D
2
to D
4
, similarly, it is possible to miniaturize size thereof.
In actual state of use where all is mounted on the printed circuit board, the V
1
+ terminal and the V
2
+ terminal are short-circuited, and the V
1
− terminal and the V
2
− terminal are short-circuited. Consequently, an anode of the thyristor and an anode gate thereof are short circuited, further, a cathode of the thyristor and a cathode gate thereof are short-circuited. Namely, under the actual state of use, sufficient high clamp voltage is maintained, latch up operation does not occur within a range of a general operating voltage of IC.
The Official gazette of the Japanese Patent Application Laid-Open No. Hei 6-69429 discloses a semiconductor circuit (a third prior art) provided with a protection device for protecting destruction of a gate oxide film of a MOS transistor (transistor for internal circuit protection) caused by static electricity and the like.
FIG. 3A
is a circuit diagram illustrating a protection circuit of a semiconductor circuit according to the third prior art, and
FIG. 3B
is a cross sectional view illustrating a region corresponding to the protection circuit.
An input pad
91
of a semiconductor circuit
90
is connected to an internal circuit
92
via a signal line
95
. A first resistor R
91
is connected between the signal line
95
and a drain of a p-channel MOS transistor Q
A
. A second resistor R
92
is connected between the signal line
95
and a drain of an n-channel MOS transistor Q
B
. A source of the transistor Q
A
and a gate thereof are connected to a power supply voltage V
PP
terminal. A source of the transistor Q
B
and a gate thereof are connected to a power supply voltage V
SS
terminal. An element separation oxide film
161
is formed between the transistors Q
A
and Q
B
. Polysilicon made resistors
162
and
163
are formed on the element separation oxide film
161
. The first resistor R
91
corresponds to the resistor
162
. The second resistor R
92
corresponds to the resistor
163
. One end of the resistor
162
is connected to a p-type diffused region
134
. One end of the resistor
Hayes & Soloway PC
Lam Tuan T.
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