Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Rectangular or pulse waveform width control
Reexamination Certificate
2001-05-02
2002-11-05
Le, Dinh T. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Rectangular or pulse waveform width control
C327S164000
Reexamination Certificate
active
06476655
ABSTRACT:
FIELD OF THE INVENTION
The invention relates to a semiconductor device, and especially to a semiconductor device provided with a memory circuit, a sense amplifier, and a delay circuit section which sets an activation period of a sense amplifier and outputs a delay output signal having a wide pulse width without using an external circuit.
BACKGROUND OF THE INVENTION
A semiconductor memory is composed of a memory circuit formed of semiconductor, a sense amplifier and a delay circuit section. When a data is read from a memory circuit, it is necessary to activate the sense amplifier at the time suited for characteristic and specification of a semiconductor device, and an operation of the sense amplifier is controlled by an output signal of the delay circuit section. A width of the output signal (a pulse width is determined by the delay circuit section. As methods for determining the width of the output pulse of the delay circuit section, flowing ones can be enumerated.
(i) The number of stages of delay elements is increased or decreased.
(ii) N-channel transistors of a depletion type (capative depletion transistors) are adopted, potentials of sources and drains are at the ground potential level, gates are respectively connected with a signal line, and dimensions of the transistors having gate capacitors are increased or decreased.
Although a pulse width of the delay circuit is 50 ns to 100 ns in general, it sometimes occurs that a wide pulse width of 200 ns to 1 ms is required because of specification of a product.
FIG. 1
shows a conventional semiconductor device disclosed in Japanese Patent Applications, Laid-Open, No. 11-220365, in which the pulse width is adjusted by means of a counter.
The semiconductor device is composed of an expected value-generating circuit
70
, a counter
71
, a comparator
72
, a delay-control circuit
73
, a delay line
74
and an invertor
75
.
The expected value-generating circuit
70
generates an expected value of the number of pulse signals of an output clock signal
17
per a period of an input clock signal
16
, and the counter
71
counts the number of the pulses of an output clock signal
17
. The comparator
72
compares a counted data of the counter
71
with the expected value outputted from the expected value-generating circuit
70
. The delay-control circuit
73
controls a value a delay on the basis of an information supplied from the comparator
72
. The delay line
74
changes the value of the delay in accordance with plural control signal Sd supplied from the delay-control circuit
73
. A ring oscillator is constituted by the delay line
74
and the invertor
75
.
Next, an operation of the structure shown in
FIG. 1
will be explained. The counter
71
counts the number of the pulses of the output clock signal
17
in a period of the input clock signal
16
. The expected value-generating circuit
70
generates a counted data of an ideal output clock signal
17
in a period of the input clock signal
16
, and inputs it to the comparator
72
as the expected value. For example, in case that an output clock signal
17
of 32 Mhz is desired to be derived from the input clock signal
16
of 32 khz, an expected value of 1000 is generated in a binary data, where 1000 is obtained from a relation that
(1/32000)/(1/32000000)=1000.
The comparator
72
compares the counted data of the counter
71
with the expected value generated by the expected value-generating circuit
70
every period of the input clock signal
16
. The comparator
72
outputs a DOWN signal when the expected value is larger, and an UP signal when the expected value is smaller. When the expected value is equal to the counted data, both the DOWN and UP signals are not outputted. When a comparison has been made in, the comparator
72
, the counter
71
is reset at once, and a next count is restarted. The delay control circuit
73
outputs n delay-control signals Sd for controlling a delay time of the delay line
74
in accordance with the UP or DOWN signal generated by the comparator
72
.
When the UP signal is outputted from the comparator
72
, the number of signals at the state of “1” in the delay-control signal Sd outputted from the delay-control circuit
73
is increased by one, and thereby the frequency of the output clock signal
17
of the ring oscillator is lowered. As a result, in a comparison made in the next period of the input clock signal
16
, the counted data of the counter
71
becomes smaller than that in the preceding period. If the expected value is smaller than the counted data of the counter
71
in a comparison made in the comparator
72
, the UP signal is again outputted and the number of the signals at the state of “1” in the plural delay-control signals Sd is further increased by one. If such processes are repeated, the expected value coincides with the counted data of the counter
71
finally.
On the other hand, if the expected value is larger than the counted data of the counter
71
as a result of a comparison made in the comparator
72
, the DOWN signal is outputted from the comparator
72
. When the DOWN signals is outputted, the frequency of the output clock signal of the ring oscillator is heightened by decreasing the number of the signals at the state of “1” in the delay control signals Sd by one. As a result, in the comparison made in the next period of the input clock signal
16
, the counted data of the counter
71
becomes larger than that in the preceding period of the same. If the expected value is still larger than the counted data of the counter
71
as the result of comparison again made in the comparator
72
, the DOWN signal is further outputted, and the number of the signals at the state of “1” in the delay control signals Sd is further decreased by one. If such processes are repeated, the expected value coincides with the counted data of the counter in a short time.
However, in the aforementioned conventional semiconductor device, the clock signal is supplied from the outside, and the delay circuit section functions on the basis of the external clock signal. That is to say, even in the semiconductor device which necessitates an inside lock signal and does not necessitate the external clock signal, it becomes necessary to supply the external clock signal to the semiconductor device, and restriction is imposed on a design of the semiconductor device.
Moreover, if becomes necessary to generate such a wide pulse as one having a width of 1 ms in accordance with specification of a user, the number of transistors for constituting the delay elements becomes more than ten times as larger as that of the ordinary semiconductor device, and areas of chips are enlarged.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the invention to provide a semiconductor device in which a delay output signal or a pulse signal can be outputted without using an external clock signal, and a pulse-generating circuit can be constituted without enlarging a scale of a circuit even if an extremely wide pulse is desired.
According to the first feature of the invention, the semiconductor device comprises:
a counter which outputs plural pulse signals in a period starting from a trigger signal and continuing for a predetermined time and generate a signal for determining an end of a delay output signal on a basis of a composed signal derived by processing the plural pulse signals, and
a delay circuit which outputs count up signals for counting up the counter on a basis of the plural pulse signals inputted from the counter and the trigger signal.
According the aforementioned structure, when the count up signals outputted from the delay circuit are inputted to the counter, the counter outputs the pulse signal for determining the end of the delay output signal as well as the plural pulse signals for setting the delay times. The plural pulse signals outputted from the counter are inputted to the delay circuit as the signals for setting the delay times, and the count up signals are generated. Since the pulse signals for setting the delay times are generated in
Le Dinh T.
McGinn & Gibb PLLC
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