Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – For plural devices
Reexamination Certificate
2001-12-21
2002-09-17
Talbott, David L. (Department: 2827)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
For plural devices
C257S724000, C257S780000
Reexamination Certificate
active
06452266
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates in general to semiconductor device packaging architectures and, in more particular, to techniques adaptable for effective use in large capacity accommodatable semiconductor devices with a plurality of chips mounted together in a single package structure.
BACKGROUND OF THE INVENTION
Investigation made by the inventors as named herein has revealed that currently available techniques for achieving increased storage capacities in modern memory package structures with multiple chips mound together in a single package may include, but not limited to, a scheme for stacking or laminating a plurality of chips in a direction along the thickness of a package, and a scheme for disposing a plurality of chips in a direction along a plane. Examples of the latter scheme are disclosed, for example, in Japanese Patent Laid-Open Nos. 17099/1999 and 256474/1998, wherein the techniques as taught by these Japanese printed publications are generally arranged as will be set forth below.
The prior known technique as taught by Japanese Patent Laid-Open No. 17099/1999 is directed to a package structure including a rectangular module substrate with four bare chips mounted thereon. The module substrate has a surface on which a linear array of conductive pads is formed at part near or around the central portion along the long sides thereof while letting chip pairs be mounted on the chip surface on the opposite sides of the pad array. Each bare chip is structurally designed to have bonding pads that are aligned in a linear array extending along the center line thereof, wherein these bonding pads and those pads on the module substrate are connected together by use of bonding wires with a resin material deposited to cover the bare chips and bonding wires.
The prior art technique suggested from Japanese Patent Laid-Open No. 256474/1998 is such that multiple bare chips are mounted on the top and bottom surfaces of a module substrate, each of which chips has a layout of center pads capable of permitting connection of wires extending from the chip center toward lateral directions, thereby providing a structure that uses bonding wires to electrically connect together bonding pads on each bare chip and the pads on the module substrate.
SUMMARY OF THE INVENTION
After consideration given to the above-identified Japanese documents, the inventors wish to make the following observations about the prior art approaches as taught thereby.
The prior art technique of Japanese Patent Laid-Open No. 17099/1999 is based on the fact that addressing terminals are useable in common among four separate chips while simultaneously enabling common use or “commonization” of control terminals including write-enable terminals and chip-enable terminals and the like, for disposing those on-substrate pads to be connected to these commonly useable or “commnizeable” terminals in the form of a linear array at a location in close proximity to the central part on the substrate, wherein this prior art fails to involve any specific teachings about how function assignment is done to respective on-substrate pads and to respective onchip pads.
The prior art of Japanese Patent Laid-Open No. 256474/1998 is inherently designed so that on-substrate chips coupled to common signals among a plurality of chips—such as address signals, control signals, power supply, or the like—are provided on the substrate in areas lying between adjacent ones of the chips mounted thereon to thereby provide connectivity of two bonding wires from both chips to these interchip pads, wherein this prior art is not stated about any exact schemes for assigning functions to respective on-substrate pads and also to onchip pads.
The present invention has been made in view of the need for function assignment to on-substrate/onchip pads such as the ones stated supra, and a primary object of the invention is to provide a new and improved semiconductor device capable of improving flexibilities of forming a pattern of electrical leads(wirings) used for electrical connection from chips via a substrate up to external terminals, by uniquely arranging the layout of addressing pads of those address signals as commonly used among four chips and also substrate structure and others.
The said and other objects, features and advantages of this invention will be apparent from the following more particular description of preferred embodiments of the invention, as illustrated in the accompanying drawings.
A brief summary of some representative ones of the inventions as disclosed herein will be explained below.
The present invention is adaptable for use in a semiconductor device that includes four chips each having on its surface a memory circuit and a plurality of pads including a plurality of address pads for use in inputting address signals of the memory circuit along with a plurality of input/output pads for inputting and outputting input/output data and also having a pair of long sides and a pair of short sides, a substrate supporting thereon the four chips and having on its surface a plurality of pads including address pads and input/output pads as electrically connected to respective ones of the address pads and input/output pads of the four chips, and a plurality of external terminals being electrically connected to the address pads and input/output pads on the substrate and including address terminals and input/output terminals as provided on a bottom surface of the substrate, which device offers specific features which follow.
More specifically the semiconductor device of this invention is characterized in that the four chips are disposed on the substrate in form of an array of rows and columns, the plurality of address pads of each of the four chips are disposed adjacent to one side of the pair of short sides, the plurality of input/output pads are disposed and spaced apart from one side of the pair of short sides toward the other side of the pair of short sides when compared to the plurality of address pads, one of the pair of short sides of each of the four chips is disposed adjacent to one of the pair of short sides of its neighboring chip to permit the plurality of address pads of each of the four chips are placed at central part on a plane of the substrate, corresponding pads in the plurality of address pads of each of the four chips are commonly connected together to the address terminals of the external terminals, and the plurality of input/output pads of each of the four chips are connected to the input/output terminals of the external terminals independently of one another in units of respective chips. With such an arrangement, it becomes possible to improve the degree of freedom or flexibility in arranging electrical wiring leads in connection between the pads on each chip and the external terminals.
In this arrangement, in order to further improve the lead wiring flexibility, the device is featured in that the substrate is of a polygonal shape having a pair of long sides and a pair of short sides, the substrate has a multilayered wiring lead structure with electrical leads of a plurality of layers, the four chips are laid out into a matrix of two rows in a direction along the short sides of the substrate and two columns in a long side direction, address pads of chips laid out in the short side direction of the substrate are electrically connected together by a first lead layer extending in the short side direction of the substrate, and address pads of chips laid out in the long side direction of the substrate are electrically connected together by a second lead layer being different from the first lead layer and extending in the long side direction of the substrate. This first lead layer is an uppermost layer among the plurality of lead layers of the substrate whereas the second lead layer is a lowermost layer among the plurality of lead layers of the substrate, wherein the first lead layer and the second lead layer are electrically connected together by more than one through-hole filled with a conductive material as formed in th
Hatano Susumu
Iwaya Akihiko
Kagaya Yutaka
Masuda Masachika
Sugano Toshio
Talbott David L.
Thai Luan
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