Semiconductor control unit

Details Semiconductor control unit Semiconductor control unit

2000-07-14

2002-06-04

Elms, Richard (Department: 2824)

Static information storage and retrieval

Addressing

Sequential

C365S194000, C345S099000

Reexamination Certificate

active

06400644

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor control unit with multiple sample-and-hold circuits, which is effectively applicable to a mobile telecommunications device like a cellular phone.
In recent years, an automated layout process of semiconductor control units, like placement and routing, has often been carried out using a hardware description language (HDL) such as Verilog.
A mobile telecommunications device such as a cellular phone uses sample-and-hold circuits for retaining a data signal therein. The automated placement and routing techniques are also frequently applied to the design of semiconductor control units of the type including sample-and-hold circuits.
FIG. 12
illustrates an overall arrangement for a known semiconductor control unit including sample-and-hold circuits. As shown in
FIG. 12
, the control unit includes switch controller
100
and sample-and-hold circuits
110
,
120
and
130
. The switch controller
100
is connected to, and sequentially outputs switch control signals SH
1
, SH
2
and SH
3
to, the sample-and-hold circuits
110
,
120
and
130
by way of signal lines
140
,
150
and
160
, respectively.
FIG. 13
illustrates a detailed circuit configuration for the known semiconductor control unit shown in FIG.
12
. The CMOS transistors
112
,
122
and
132
, functioning as switches (which will be herein called “CMOS switches”), of the sample-and-hold circuits
110
,
120
and
130
sequentially open in response to the switch control signals SH
1
, SH
2
and SH
3
provided from the switch controller
100
, respectively. Synchronously with these switch control signals SH
1
, SH
2
and SH
3
, data, received at an input terminal DATAIN, is sampled in capacitors
111
,
121
and
131
of the sample-and-hold circuits
110
,
120
and
130
in this order.
FIG. 14
is a timing diagram illustrating this operation. As shown in
FIG. 14
, first, the switch control signal SH
1
rises to the H level at a time T
1
, when the CMOS switch
112
of the sample-and-hold circuit
110
opens and the data starts being stored into the capacitor
111
. Thereafter, when the switch control signal SH
1
falls to the L level at a time T
2
, the data is sampled and held in the capacitor
111
and the CMOS switch
112
closes.
Next, the switch control signal SH
2
rises to the H level at a time T
3
, when the CMOS switch
122
of the sample-and-hold circuit
120
opens and the data starts being stored into the capacitor
121
. Thereafter, when the switch control signal SH
2
falls to the L level at a time T
4
, the data is sampled and held in the capacitor
121
and the CMOS switch
122
closes.
In the same way, when the switch control signal SH
3
rises to the H level at a time T
5
, the CMOS switch
132
of the sample-and-hold circuit
130
opens and the data starts being stored into the capacitor
131
. Next, when the switch control signal SH
3
falls to the L level at a time T
6
, the data is sampled and held in the capacitor
131
and the CMOS switch
132
closes. In this manner, the multiple CMOS switches
112
,
122
and
132
open and close in turns and the data received at the input terminal DATAIN is sequentially stored into the sample-and-hold circuits
110
,
120
and
130
in this order.
Thanks to the recent development of automated placement and routing techniques applicable to the design process of semiconductor devices, the wire lengths of signal lines are now controllable much more precisely than what they used to be. Actually, though, chips fabricated are not exactly the same ones, but show slightly different characteristics one from the other as for the resistance and capacitance of their signal lines. As a result, a signal cannot be transmitted through those lines at an intended transfer rate, either, thus causing signal propagation delays.
FIG. 15
is a timing diagram illustrating a situation where the signal propagation delays are caused. As shown in
FIG. 15
, the data received at the input terminal DATAIN is superposed with crosstalk noise of a digital signal caused by the switching of the CMOS switches
112
,
122
and
132
. In addition, the data is also affected by switching noise that has reached after having made a detour inside the substrate.
First, suppose the fall of the switch control signal SH
1
has been delayed. In that case, if the next switch control signal SH
2
rose to the H level at the time T
2
before the switch control signal SH
1
falls to the L level at the time T
3
, then the CMOS switch
122
opens at the time T
2
. In such a situation, the data received at the input terminal DATAIN is superposed with switching noise. And when the switch control signal SH
1
finally falls to the L level at the time T
3
, the data received at the input terminal DATAIN is sampled and held in the capacitor
111
. However, the switching noise &Dgr;V, which was caused due to the switching of the CMOS switch
122
, is also sampled and held erroneously in the capacitor
111
.
Next, suppose the fall of the switch control signal SH
2
has also been delayed. In that case, if the next switch control signal SH
3
rose to the H level at the time T
4
before the switch control signal SH
2
falls to the L level at the time T
5
, then the CMOS switch
132
opens at the time T
4
to cause switching noise. And when the switch control signal SH
2
finally falls to the L level at the time T
5
, the data received at the input terminal DATAIN is sampled and held in the capacitor
121
. However, the switching noise &Dgr;V, which was caused due to the switching of the CMOS switch
132
, is also sampled and held erroneously in the capacitor
121
. As can be seen, switching noise adversely deteriorates the sample-and-hold performance of the known control unit.
SUMMARY OF THE INVENTION
It is therefore an object of the invention to improve the sample-and-hold performance by getting data sampled and held accurately with no switching noise introduced thereto. To achieve this object, while the data is being sampled and held in one of sample-and-hold circuits, a switch in the next sample-and-hold circuit is not allowed to open even if the wire lengths of signal lines between a switch controller and the sample-and-hold circuits are different from each other.
That is to say, according to the present invention, a switch included in one of the sample-and-hold circuits is never allowed to open until the data has been completely held in the previous one of the sample-and-hold circuits.
An inventive semiconductor control unit includes multiple sample-and-hold circuits for storing externally input data therein. Each said sample-and-hold circuit includes a switch for selectively passing the data therethrough. The control unit further includes a controller, connected to the sample-and-hold circuits through respective signal lines, for sequentially outputting switch control signals to the sample-and-hold circuits to get the data stored in one of the sample-and-hold circuits after another. The control unit further includes the same number of switching circuits as the sample-and-hold circuits. The switching circuits are provided for the respective signal lines. Each said switching circuit receives not only a first one of the switch control signals from the controller through its associated signal line but also a state signal from another one of the switching circuits that received a second one of the switch control signals that precedes the first switch control signal. And while the switch of another one of the sample-and-hold circuits that received the second switch control signal is opened, the switching circuit is not allowed to output the first switch control signal to associated one of the sample-and-hold circuits.
In one embodiment of the present invention, each said switching circuit does not output the first switch control signal to the associated sample-and-hold circuit until the switching circuit receives a CLOSED signal as the state signal from the another one of the switching circuits that received the second switch control signal.
In ano

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