Semiconductor control line address decoding circuit

Details Semiconductor control line address decoding circuit Semiconductor control line address decoding circuit

2011-06-28

2011-06-28

Nguyen, Tuan T. (Department: 2824)

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

C365S230020

Reexamination Certificate

active

07969812

ABSTRACT:
Apparatus and method for decoding addresses of control lines in a semiconductor device, such as a solid state memory (SSM). In accordance with some embodiments, a switching circuit includes an array of switching devices coupled to 2Noutput lines and M input lines, wherein M and N are respective non-zero integers and each output line has a unique N-bit address. A decoder circuit coupled to the switching circuit divides the N-bit address for a selected output line into a plurality of multi-bit subgroup addresses, and asserts the M input lines in relation to respective bit values of said subgroup addresses to apply a first voltage to the selected output line and to concurrently apply a second voltage to the remaining 2N-1 output lines.

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