Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive...
Reexamination Certificate
2002-06-21
2004-08-24
Nguyen, Tuan H. (Department: 2813)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
C438S424000, C438S430000
Reexamination Certificate
active
06780728
ABSTRACT:
TECHNICAL FIELD
The invention pertains to semiconductor constructions, and methods of forming semiconductor constructions. In particular applications, the invention pertains to methods of forming isolation regions associated with a semiconductor substrate.
BACKGROUND OF THE INVENTION
There is a continuing demand for increasing the circuit device density associated with semiconductor constructions. Such is generating a continuing demand for improved isolating structures between adjacent circuit devices.
Trench isolation is a fairly typical method of electrically isolating adjacent circuit devices from one another. Trench isolation utilizes a trench etched into a semiconductor substrate between adjacent circuit devices (such as, for example, between memory cells in a DRAM array). The trench is filled with a suitable material to create a physical barrier to current conduction between the adjacent circuit devices.
A material that can be provided within a trench is silicon, such as, for example, polycrystalline silicon, and such material can be separated from a semiconductor substrate comprising the trench (such as, for example, a monocrystalline silicon substrate) by an insulative material formed within a periphery of the trench. There can be advantages to utilizing silicon in a trench isolation region because silicon can be deposited highly-conformally across a substrate. However, various disadvantages are also found to occur. One of the disadvantages is that junction leakage can occur when heavily-doped diffusion regions are proximate the trench isolation region, as doped silicon in the trench can act as a gated diode. The junction leakage can cause numerous problems with semiconductor circuitry utilizing the conductively-doped diffusion regions. For instance, if the conductively-doped diffusion regions are associated with a dynamic random access memory (DRAM) cell, the junction leakage can be detrimental to DRAM retention time.
It would be desirable to develop improved isolation regions, and methodology for forming such isolation regions.
SUMMARY OF THE INVENTION
In one aspect, the invention encompasses an isolation region formed within a semiconductive material. The semiconductive material has a surface and an opening extending through the surface. An electrically insulative liner is provided along a periphery of the opening, and subsequently a mass is formed within a bottom portion of the opening. The mass comprises a mid-gap work function, and in exemplary applications comprises a refractory metal (such as Mo, W, molybdenum silicide or tungsten silicide), silicon (either doped or undoped), and/or SiGe. The mass has a top surface which is recessed beneath the surface of the semiconductive material. An electrically insulative layer is within the opening and over the top surface of the mass.
In one aspect, the invention encompasses a semiconductor construction. The construction includes a first semiconductive material having a surface and an opening extending through the surface. A first electrically insulative material is provided along a periphery of the opening, and subsequently a second semiconductive material is formed within a bottom portion of the opening. The second semiconductive material is separated from the first semiconductive material by the insulative material. The second semiconductive material has a top surface at least about 200 Angstroms beneath the surface of the first semiconductive material. A second electrically insulative material is within the opening and over the top surface of the second semiconductive material.
In one aspect, the invention encompasses a method of forming a semiconductor construction. A first semiconductive material is provided, and such material has a surface and an opening extending through the surface. The first semiconductive material is background doped with a first type dopant. At least one conductively-doped diffusion region extends into the first semiconductive material in a location proximate the opening. The conductively-doped diffusion region extends to a depth within the first semiconductive material and comprises a second-type majority dopant. A second semiconductive material is formed within the opening to partially fill the opening. An insulative material is formed within the opening and over the top surface of the second semiconductive material. The second semiconductive material has a top surface elevationally below the depth of the conductively-doped diffusion region.
REFERENCES:
patent: 4766090 (1988-08-01), Coquin et al.
patent: 5099304 (1992-03-01), Takemura et al.
patent: 6037239 (2000-03-01), Jennings
patent: 6096621 (2000-08-01), Jennings
patent: 6130140 (2000-10-01), Gonzalez
patent: 6133105 (2000-10-01), Chen et al.
patent: 6133116 (2000-10-01), Kim et al.
patent: 6277709 (2001-08-01), Wang et al.
patent: 6440793 (2002-08-01), Divakaruni et al.
patent: 6465325 (2002-10-01), Ridley et al.
patent: 2002/0076879 (2002-06-01), Lee et al.
patent: 2002/0196651 (2002-12-01), Weis
patent: 2003/0013272 (2003-01-01), Hong et al.
COB Stack DRAM Cell Technology beyond 100 nm Technology Node; Yongjik Park & Kinam Kim; pp. 349.1-349.3.
Micro)n Technology, Inc.
Nguyen Tuan H.
Wells St. John P.S.
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