Semiconductor device manufacturing: process – Gettering of substrate
Reexamination Certificate
2002-04-26
2003-07-29
Lebentritt, Michael S. (Department: 2824)
Semiconductor device manufacturing: process
Gettering of substrate
C438S474000, C438S510000, C438S526000, C438S527000
Reexamination Certificate
active
06599817
ABSTRACT:
TECHNICAL FIELD
The invention pertains to semiconductor constructions comprising damage (or gettering) regions; and also pertains to methods of forming semiconductor constructions comprising damage (or gettering) regions.
BACKGROUND OF THE INVENTION
Impurity contamination of active area semiconductive materials is a problem within the semiconductor industry. Of particular concern are metallic contaminants, such iron, nickel and copper. When such impurities are present in semiconductive material of a device, the impurities can degrade the characteristics and reliability of the device. As integration in semiconductor devices becomes increasingly dense, the tolerance for metallic contaminants becomes increasingly stringent.
Among the methods for decreasing metallic contamination in semiconductor wafers are methods for improving cleanliness in semiconductor device manufacturing plants. However, regardless of how many steps are taken to insure clean production of semiconductor devices, some degree of contamination by metals seems inevitable. Accordingly, it is desirable to develop methods and structures for isolating metallic contaminants present in semiconductor wafers from devices which are ultimately formed within and upon such wafers. The act of isolating these contaminants is generally referred to as gettering, as the contaminants are gathered (typically physically and/or chemically), or gettered, to specific areas (referred to as “proximity gettering regions”) within a semiconductor wafer.
Conventional processes for gettering metallic contaminants often focus on creating defects or damage within a semiconductor wafer in a region where gettering is sought to occur. Example embodiments of prior art methods for forming gettering regions are shown and described in U.S. Pat. Nos. 6,339,011 and 5,773,356, both of which are hereby incorporated by reference.
The methods described in U.S. Pat. Nos. 5,773,356 and 6,339,011 form damage regions within bulk semiconductive materials, with an exemplary bulk material being a bulk monocrystalline silicon wafer. The monocrystalline silicon wafer can be lightly background doped with p-type and/or n-type material. The wafer can be referred to as a semiconductor substrate. To aid in interpretation of the claims that follow, the terms “semiconductive substrate” and “semiconductor substrate” are defined to mean any construction comprising semiconductive material, including, but not limited to, bulk semiconductive materials such as a semiconductive wafer (either alone or in assemblies comprising other materials thereon), and semiconductive material layers (either alone or in assemblies comprising other materials). The term “substrate” refers to any supporting structure, including, but not limited to, the semiconductive substrates described above.
A damage region can be formed within a semiconductive material substrate by implanting a neutral conductivity type dopant into the semiconductive material of the substrate. Exemplary neutral conductivity type dopants are H
2
, He, Ge, Ar, Si, O, C and N. The implanting of the dopants can be conducted at an energy of less than 1.0 MeV and at a current density of from 0.5 A/cm
2
to 3.5 A/cm
2
. The damage formed within the One or more conductivity-enhancing dopants can be implanted around the damage region during incorporation of the damage region into a proximity gettering region. For instance, one or both of phosphorous and boron can be implanted into an area surrounding the damage region.
FIGS. 1 and 2
illustrate a cross-sectional view and top view, respectively, of a prior art proximity gettering region formed within a semiconductive material wafer. More specifically,
FIGS. 1 and 2
illustrate a construction
10
comprising a semiconductive material substrate
12
. The semiconductive material substrate
12
can be, for example, monocrystalline silicon lightly-doped with a background p-type dopant.
A proximity gettering region
14
is formed within substrate
12
. Gettering region
14
comprises a damage region
16
and a conductively-doped region
18
surrounding region
16
. Damage region
16
can be formed by, for example, implanting a neutral-type dopant into substrate
12
. The implant disrupts a lattice of the semiconductive material to form extended crystal lattice defects within the semiconductive material. The defects can comprise, consist essentially of, or consist of vacancies in the crystalline lattice, and the term “extended” indicates that the defects are larger than point defects. It is desirable that the implant utilized to form the damage region is at a low enough dose and duration that the crystalline semiconductive material is not appreciably converted to an amorphous form by the implant, and yet is at a high enough dose and duration to form the desired extended lattice defects. It is also desired that the defects be stable to a thermal budget less than or equal to that utilized in convention CMOS processing.
Doped region
18
can be formed by implanting a conductivity enhancing dopant into material
12
at a suitable depth to surround the damage region. The conductivity enhancing dopant of region
18
can be an opposite-type to that utilized in the background doping of material
12
. Accordingly, if material
12
is background-doped with a p-type dopant, region
18
can be doped with an n-type dopant (such as, for example, phosphorous). Alternatively, if substrate
12
is background-doped with an n-type dopant, region
18
can be doped with a p-type dopant (such as, for example, boron).
Substrate
12
comprises an upper surface
15
, and gettering region
14
is typically formed at a depth “D” of greater than 4 microns beneath upper surface
15
. Gettering region
14
can be formed at such depth by implanting dopants through upper surface
15
and into the material
12
to a desired depth. Alternatively, a substrate can initially be provided to have an upper surface approximately coextensive with the location where gettering region
14
is ultimately to be formed. Gettering region
14
can then be formed by a shallow implant into the substrate to form the gettering region along the upper surface of the substrate. Subsequently, additional monocrystalline material can be epitaxially formed over the gettering region
14
to provide the material between gettering region
14
and upper surface
15
.
Ultimately, various devices are formed to be supported by substrate
12
. The devices can be formed over the substrate, and further can comprise portions within the substrate. For instance, the devices can include transistor devices having gates formed over the substrate and source/drain regions formed within the substrate. Various devices are illustrated diagrammatically in
FIGS. 1 and 2
by blocks
20
and
22
. Block
20
can correspond to a plurality of devices which are to be protected from metallic contaminants by gettering region
14
. Such devices can include, for example, memory devices, and such would typically be arranged in an array. Exemplary memory devices are dynamic random access memory (DRAM) devices. As another example, the devices
20
can correspond to FLASH devices, such as, for example, erasable programmable read only memory (EPROM) and electrically erasable programmable read only memory (EEPROM) devices.
As block
20
is a simplified schematic representation of devices, it can accordingly be referred to herein as devices
20
. Further, in various applications block
20
can be considered a simplified schematic of an array of devices (such as memory devices), and in such applications block
20
can be considered an array
20
.
Block
22
can be, in particular aspects, considered a simplified schematic representation of devices associated with a charge pump, and accordingly block
22
can be referred to herein as a charge pump
22
. The charge pump generates electrons which are directed into substrate
12
to maintain a desired potential within the substrate. The electrons are illustrated diagrammatically by wavy lines
24
and
26
within FIG.
1
.
A problem which can o
Lebentritt Michael S.
Wells St. John P.S.
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