Semiconductor constructions

Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Including dielectric isolation means

Reexamination Certificate

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Details

C257S499000, C257S510000, C257S513000, C257S288000, C257S368000

Reexamination Certificate

active

08035189

ABSTRACT:
The invention includes methods of forming oxide structures under corners of transistor gate stacks and adjacent trenched isolation regions. Such methods can include exposure of a semiconductor material to steam and H2, with the H2being present to a concentration of from about 2% to about 40%, by volume. An oxide structure formed under the bottom corner of a transistor gate stack can have a bottom surface with a topography that includes a step of at least about 50 Å, and an upper surface directly over the bottom surface and having a topography that is substantially planar. Methodology of the present invention can be utilized to form semiconductor constructions suitable for incorporation into highly integrated circuitry. The highly integrated circuitry can be incorporated into electronic systems, and can, for example, be utilized in processors and/or memory storage devices.

REFERENCES:
patent: 6027982 (2000-02-01), Peidous et al.
patent: 7781860 (2010-08-01), Smith et al.
patent: 2002/0197823 (2002-12-01), Yoo et al.
patent: 2005/0136588 (2005-06-01), Speyer
Balasubramanian, N. et al., “Active Corner Engineering in the Process Integration for Shallow Trench Isolation”, J. Vac.Sci.Technol. B 18(2), Mar./Apr. 2000, pp. 700-705.
Tung, C. et al, ULSI Semiconductor Technology Atlas, Wiley-Interscience 2003, Chap. 6.5 “Shallow Trench Isolation (STI)” pp. 235-249.

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