Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Including dielectric isolation means
Reexamination Certificate
2008-01-14
2009-06-30
Le, Thao P. (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Including dielectric isolation means
C257SE21304
Reexamination Certificate
active
07554171
ABSTRACT:
The invention includes a method of forming a planarized surface over a semiconductor substrate. A substrate is provided which includes a memory array region and a peripheral region proximate the memory array region. The memory array region has a higher average elevational height than the peripheral region. Polysilazane is formed over the memory array region and over the peripheral region. The polysilazane is densified. A material is formed over the polysilazane. The material is planarized while using the densified polysilazane as a stop. The planarization forms a planarized surface which extends over the memory array and peripheral regions. The planarized surface comprises both the densified polysilazane and the material.
REFERENCES:
patent: 5169491 (1992-12-01), Doan
patent: 5618381 (1997-04-01), Doan et al.
patent: 5665657 (1997-09-01), Lee
patent: 6184143 (2001-02-01), Ohashi et al.
patent: 6187662 (2001-02-01), Usami et al.
patent: 6215144 (2001-04-01), Saito et al.
patent: 6225240 (2001-05-01), You et al.
patent: 6235620 (2001-05-01), Saito et al.
patent: 6258649 (2001-07-01), Nakamura et al.
patent: 6261883 (2001-07-01), Koubuchi et al.
patent: 6399438 (2002-06-01), Saito et al.
patent: 6432843 (2002-08-01), Kim et al.
patent: 6479405 (2002-11-01), Lee et al.
patent: 6489252 (2002-12-01), Goo et al.
patent: 6596607 (2003-07-01), Ahn
patent: 6635586 (2003-10-01), Goo et al.
patent: 6649503 (2003-11-01), Kim et al.
patent: 6693050 (2004-02-01), Cui et al.
patent: 2001/0012687 (2001-08-01), Xu et al.
patent: 2003/0013387 (2003-01-01), Tsai et al.
patent: 2003/0062599 (2003-04-01), Egami et al.
patent: 2004/0106292 (2004-06-01), Sato et al.
patent: 2004/0222740 (2004-11-01), Kim
patent: 2004/0224496 (2004-11-01), Cui et al.
patent: 2004/0263711 (2004-12-01), Matsumoto et al.
patent: 2005/0037529 (2005-02-01), Nagao et al.
patent: 2005/0087772 (2005-04-01), Yamazaki
patent: 2005/0266650 (2005-12-01), Ahn et al.
Le Thao P.
Micro)n Technology, Inc.
Wells St. John P.S.
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