Semiconductor connection component

Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor

Reexamination Certificate

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Details

C438S123000, C438S197000, C257SE21006, C257SE21051, C257SE21077, C257SE21499

Reexamination Certificate

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07968370

ABSTRACT:
There is a need for providing a technology capable of decreasing on-resistance of a power transistor in a semiconductor device that integrates the power transistor and a control integrated circuit into a single semiconductor chip. There is another need for providing a technology capable of reducing a chip size of a semiconductor device. A semiconductor chip includes a power transistor formation region to form a power transistor, a logic circuit formation region to form a logic circuit, and an analog circuit formation region to form an analog circuit. A pad is formed in the power transistor formation region. The pad and a lead are connected through a clip whose cross section is larger than that of a wire. On the other hand, a bonding pad is connected through the wire29.

REFERENCES:
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patent: 2004/0080028 (2004-04-01), Yanagisawa et al.
patent: 2007/0035019 (2007-02-01), Carney et al.
patent: 2007/0040187 (2007-02-01), Koike et al.
patent: 2007/0040260 (2007-02-01), Otremba
patent: 2007/0075409 (2007-04-01), Letterman et al.
patent: 2007/0111393 (2007-05-01), Burghout et al.
patent: 2007/0114676 (2007-05-01), Anderson et al.
patent: 11-204724 (1999-07-01), None
patent: 2000-49184 (2000-02-01), None
patent: 2004-153234 (2004-05-01), None

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