Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Junction field effect transistor
Reexamination Certificate
1999-12-23
2001-05-15
Crane, Sara (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Junction field effect transistor
C257S266000, C257S287000, C257S260000
Reexamination Certificate
active
06232625
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The invention relates to a semiconductor configuration that is suitable for passively limiting an electric current, and also to the use of such a semiconductor configuration.
In order to supply an electrical load (apparatus) with an electric current, the load is connected to a line branch of an electrical supply network via a switching device. In order to protect the load against excessively high currents, in particular in the event of a short circuit, in low-voltage switching technology use is made of a switching device having a disconnector, which protects the line branch and for which a fuse is generally used, and having a mechanical power circuit-breaker having a switching time of distinctly more than one millisecond (1 ms). If a plurality of loads are operated simultaneously in a line branch and a short circuit occurs in only one of these loads, then it is highly advantageous if the loads which are not affected by the short circuit can continue to operate without disruption and only the load affected by the short circuit is switched off. For this purpose, current-limiting components (“limiters”) are necessary that are connected directly upstream of each load and in each case reliably limit the current of the prospective short-circuit current to a predetermined, noncritical overcurrent value within a time of distinctly less than 1 ms and, consequently, before the tripping of the disconnector provided for the line branch. Furthermore, the current-limiting components should operate passively without the need for being driven and be able to withstand the voltages that are present in the current-limiting situation and are usually as much as 700 V, and sometimes as much as 1200 V. Since the power loss then arising in the component is very high, it would be particularly advantageous if, in addition, the passive current limiter automatically reduced the current to values distinctly below the predetermined over-current value with the additional take-up of voltage (intrinsically safe component).
The only passive current limiter that is commercially available is the apparatus which is described in the paper “Polyäthylen-Stromwächter für den Kurzschlu&bgr;schutz” [Polyethylene Current Monitor For Short-Circuit Protection] by T. Hansson, ABB Technik 4/92, pages 35-38 and having the product name PROLIM, which is based on a current-dependent conductivity of the grain boundaries of the material used in this apparatus. However, if the apparatus is used relatively frequently for current limiting, a change may occur in the current saturation value at which the current is limited.
Otherwise, it is generally the case that only active current limiters are used, which detect the current and limit it by active control in the event of a predetermined maximum current value being exceeded. Published, Non-Prosecuted German Patent Application DE 43 30 459 A discloses such an active, semiconductor-based current limiter. The latter has a first semiconductor region of a predetermined conduction type, to which a respective electrode is assigned on surfaces that are remote from one another. In the first semiconductor region, further semiconductor regions of the opposite conduction type are disposed spaced apart from one another between the two electrodes. Respective channel regions of the first semiconductor region are formed between the further semiconductor regions, the channel regions being directed perpendicularly with respect to the two surfaces of the first semiconductor region (vertical channels). A vertical current flow between the two electrodes is guided through the channel regions and thereby limited. In order to control the current flow between the two electrodes, a gate voltage is applied to the oppositely doped semiconductor regions in the first semiconductor region and controls the resistances of the channel regions.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a semiconductor configuration and use thereof which overcomes the above-mentioned disadvantages of the prior art devices of this general type, which can be used for passively limiting electric currents in the event of a critical current value being exceeded. The intention is also to specify a current limiter configuration having such a semiconductor configuration.
With the foregoing and other objects in view there is provided, in accordance with the invention, a semiconductor configuration, including:
a first semiconductor region having a first surface and at least one contact region disposed at the first surface;
at least one second semiconductor region forming a first p-n junction with the first semiconductor region and the first p-n junction having a depletion zone;
at least one third semiconductor region disposed at the first surface of the first semiconductor region forming a second p-n junction with the first semiconductor region and the second p-n junction having a depletion zone, the at least one third semiconductor region having a second surface not adjoining the first semiconductor region;
a first electrode making contact with both the at least one contact region of the first semiconductor region and with the at least one third semiconductor region at the second surface; and
a second electrode making contact with the first semiconductor region, the first semiconductor region having at least one channel region lying in a current path between the first electrode and the second electrode, the at least one the channel region being pinched off by the depletion zone of the first p-n junction and the depletion zone of the second p-n junction if a predetermined saturation current is reached between the first electrode and the second electrode, after which a current is limited to a limit current below the predetermined saturation current.
With the foregoing and other objects in view there is further provided, in accordance with the invention, a semiconductor configuration, including:
a first semiconductor region having a first surface and at least one contact region disposed at the first surface;
at least one second semiconductor region forming a p-n junction with the first semiconductor region and the p-n junction having a depletion zone;
a first electrode forming an ohmic contact on the at least one contact region of the first semiconductor region, the first electrode also forming a Shottky contact having a depletion zone on a region of the first semiconductor region which lies outside the at least one contact region; and
a second electrode making contact with the first semiconductor region, the first semiconductor region having at least one channel region lying in a current path between the first electrode and the second electrode, the at least one channel region being pinched off by the depletion zone of the p-n junction and the depletion zone of the Shottky contact when a predetermined saturation current is reached between the first electrode and the second electrode, after which a current is limited to a limit current below the predetermined saturation current.
These semiconductor configurations automatically limit a current, in particular a short-circuit current, to an acceptable current value, the reverse current (limit current), by an advantageous combination of physical effects in the channel region.
In a particularly advantageous embodiment of the semiconductor configuration, this embodiment also being particularly resistant to breakdown, the second semiconductor region is disposed within the first semiconductor region below the contact region and runs further than the contact region in all directions parallel to the surface of the first semiconductor region. Owing to the charge storage in the second semiconductor region and the resulting persistent pinching-off of the channel region even in the event of subsequent voltage decreases at the two electrodes, the semiconductor configuration is now able essentially to maintain the reverse current as an acceptable current value over a predetermined blocking time (limiting time).
Th
Bartsch Wolfgang
Mitlehner Heinz
Stephani Dietrich
Crane Sara
Greenberg Laurence A.
Lerner Herbert L.
SiCED Electronics Development GmbH & Co. KG
Stemer Werner H.
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