Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum
Reexamination Certificate
1999-09-07
2002-08-06
Weiss, Howard (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified material other than unalloyed aluminum
Reexamination Certificate
active
06429520
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention lies in the semiconductor technology field. More specifically, the invention relates to a semiconductor component having at least local silicon wiring and to a method of fabricating the semiconductor component.
Integrated circuits, in particular CMOS circuits, are fabricated with a plurality of process steps. The fabrication costs of the circuits are thereby determined by the processing complexity and the physical processing time. Highly complex modules frequently require several hundred individual process steps and a number of days for the processing run of the product.
Some of the process steps must be provided for the purpose of producing the wiring which connects the individual active components to one another and ensures the connection of the integrated circuit to the “exterior.” The wiring is usually realized by means of one or more conductor levels made of aluminum.
However, there are applications in which a conductor level made of aluminum is, in the first instance, too expensive and, in the second instance, requires too much space. In order to overcome this problem, local connections made of polysilicon, silicide or polycide are usually used. In that context, European published patent application EP 0 208 267 describes a static read-write memory (SRAM) in which the “gate level,” comprising doped polysilicon and metal silicide, is used as an additional local wiring level for the cross coupling between n-type and p-type channel transistors. In rare cases, polysilicon is also used as a complete, global wiring level in pure NMOS technologies.
However, when CMOS circuits are realized with polysilicon wiring a series of difficulties occur. For instance, the n+ source/drain zones of n-channel transistors are connected to the p+ source/drain zones of p-type channel transistors with polysilicon tracks. In order to permit good contact to be brought about between an n+ diffusion zone and a polysilicon track, the polysilicon track must also have n-type doping at the contact point. On the other hand, in order to permit good contact to be brought about between a p+ diffusion zone and a polysilicon track the polysilicon track must have p-type doping at the contact point. As a result of this it is necessary to connect an n-type conductive polysilicon region to a p-type conductive polysilicon region somewhere on the path from the n+ diffusion zone to the p+ diffusion zone. The pn-junction which occurs here leads to high contact resistances which severely restricts the use of polysilcon wiring. Moreover, in the so-called “dual gate technique” of modern CMOS technology both p+ and n+ doped gates made of polysilicon, which are structured on one level, are used. If different gates are then connected by a polysilicon track, pn-junctions occur once more and have to be bridged.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a semiconductor component having at least local polysilicon wiring and a method of producing the component, which overcomes the above-mentioned disadvantages of the heretofore-known devices and methods of this general type and which significantly reduces the above-noted problems.
With the foregoing and other objects in view there is provided, in accordance with the invention, a semiconductor component with local silicon wiring, comprising:
a first silicon region doped with a dopant of a first conductivity type;
a second silicon region doped with a dopant of a second conductivity type and disposed at least partially above the first silicon region;
an insulation layer between the first silicon region and the second silicon region, the insulation layer having an opening formed therein; and
a conductive layer made of a material selected from the group consisting of metal, metal nitride, and a combination thereof and disposed in vicinity of the opening formed in the insulation layer, the conductive layer electrically connecting the first silicon region with the second silicon region via the opening.
By using a metal and/or metal nitride layer it is possible for pn-type junctions which occur between differently doped silicon regions to be bridged, or for the metal layers and/or metal nitride layers to be arranged between the silicon regions, in such a way that a pn-type junction is not even formed. This also makes it possible to realize a complete global wiring level made of silicon in a CMOS circuit without the function of this wiring level being disrupted by the increased contact resistances which would occur otherwise and which are caused by the pn-type junctions. In this way, it is possible to dispense with one metallization level, which has a positive effect both on the process complexity and on the area which the CMOS circuit requires.
Furthermore, wiring made of silicon, which is preferably composed of polysilicon, makes external manipulation or subsequent analysis of a circuit considerably more difficult. In order to be able to carry out manipulations to an integrated circuit, it is usually necessary firstly to analyze the integrated circuit. To do this, the passivation layer or the insulation layers between the wiring levels must firstly be removed layer by layer so that the wiring levels which are exposed in this way can be examined. However, the chemical processes which have to be used to remove the insulation layers, in particular PSG and BPSG, also attack the metal layer and/or metal nitride layer and remove this as well. As a result, it is no longer possible to tap an electrical signal on an exposed wiring level, which makes it virtually impossible to analyze the integrated circuit.
Titanium, tantalum or tungsten are preferably used as the metal and their nitrides as the metal nitrides. In particular, these materials exhibit good electrical conductivity, have excellent adhesion to silicon and act as a diffusion barrier for the dopants which are located in the adjoining silicon regions. The conductive layer can be formed here as a pure metal layer, pure metal nitride layer or as a combination of metal layer and metal nitride layer. Pure metal nitride layers and a combination of metal layer and metal nitride layer are particularly preferred. It is favorable to select the combination of metal and associated metal nitride.
The semiconductor component according to the invention thus makes possible applications in which the important factors are cost-effective production and a high degree of protection against external manipulation. Processors for chip cards and smart cards are an example of such an application. The processors for chip cards must, in the first instance, be cheap so that as many fields of application for a chip card can be exploited economically. On the other hand, chip cards are frequently used in access supervision systems or in electronic payment transactions so that they have to be as resistant as possible to unauthorized manipulation. The silicon wiring is implemented here as polysilicon wiring for reasons of cost and to simplify fabrication.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a semiconductor component having silicon wiring and a method for fabricating said component, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.
REFERENCES:
patent: 4888306 (1989-12-01), Komatsu et al.
patent: 4890141 (1989-12-01), Tang et al.
patent: 5654589 (1997-08-01), Huang et al.
patent: 5940151 (1999-08-01), Ha
patent: 6138686 (2000
Kakoschke Ronald
Stokan Regina
Greenberg Laurence A.
Mayback Gregory L.
Siemens Aktiengesellschaft
Stemer Werner H.
Trinh (Vikki) Hoa B.
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