Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Making plural separate devices
Reexamination Certificate
2003-06-10
2004-12-07
Graybill, David E. (Department: 2827)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Making plural separate devices
C462S080000, C462S080000, C462S902000
Reexamination Certificate
active
06828175
ABSTRACT:
FIELD OF THE INVENTION
This invention relates generally to semiconductor manufacture and packaging. More particularly, this invention relates to a semiconductor component with backside contacts, to a method for fabricating the component, and to systems incorporating the component.
BACKGROUND OF THE INVENTION
Semiconductor components, such as chip scale packages and bumped dice, are being manufactured with a smaller outline and with a higher pin count than conventional plastic or ceramic packages. This type of semiconductor component typically includes a dense area array of terminal contacts, such as solder bumps in a ball grid array (BGA) or metal pins in a pin grid array (PGA). The terminal contacts permit the component to be surface mounted to a supporting substrate, such as a package substrate, a module substrate or a circuit board.
The quality, reliability and cost of these types of components is often dependent on the fabrication method. The formation of the terminal contacts and the electrical paths between the terminal contacts and the dice are a particular concern. In particular, reliable electrical interconnections must be made between the terminal contacts for the component, and contacts on the dice contained within the component. Typically, the die contacts comprise thin film aluminum bond pads in electrical communication with integrated circuits on the dice.
Some prior art components require relatively complicated interconnections, such as metal beams or wires, formed of gold, gold plated materials, aluminum, copper or solder using a bonding process, such as thermosonic bonding or wire bonding. The interconnections, and their bonds with the die contacts and the terminal contacts, are subjected to stresses during manufacture, and during subsequent use of the component. These stresses can cause the interconnections to weaken or pull apart, adversely affecting the reliability of the components.
The present invention is directed to an improved semiconductor component having novel backside contacts and conductive member interconnections. In addition, the present invention is directed to a novel wafer level fabrication method for manufacturing the component in volume using conventional equipment.
SUMMARY OF THE INVENTION
In accordance with the present invention, an improved semiconductor component, a method for fabricating the component, and electronic assemblies incorporating the component are provided.
The component includes a semiconductor die having a thinned semiconductor substrate with a circuit side (front side) and a back side. The die includes integrated circuits and a pattern of die contacts on the circuit side in electrical communication with the integrated circuits. In a first embodiment (male version), the component includes an array of pin contacts on the backside, and conductive members in the substrate in electrical communication with the die contacts and the pin contacts. Each conductive member is formed by an opening in a die contact and substrate and a conductive material in the opening. In addition, each conductive member is exposed on the back side of the substrate to form a pin contact. The component can also include redistribution conductors and contacts on the circuit side in electrical communication with the conductive members.
In a second embodiment (female version) the conductive members comprise openings having insulated sidewalls plated with a conductive material. In this embodiment the conductive members are configured for mating physical and electrical engagement with a pin contact on an adjacent component of a stacked assembly.
The method for fabricating the component includes the step of providing multiple semiconductor dice on substrate, such as a semiconductor wafer, having a circuit side and a back side. The method also includes the steps of forming openings in the die contacts and part way through the substrate, forming an electrically insulating passivation layer on the circuit side and in the openings, and depositing a conductive material in the openings to form the conductive members. In addition, the method can include the steps of thinning and etching the substrate from the back side to expose terminal portions of the conductive members forming the pin contacts, and then singulating the dice from the wafer. The method can also include the steps of forming redistribution conductors on the circuit side in electrical communication with the conductive members and circuit side contacts on the redistribution conductors.
With the method the pin contacts are formed on the back side of the component using steps performed predominantly on the circuit side of the component. Advantageously, the pin contacts provide electrical connection points for performing various wafer level test procedures. In addition, the component can be integrated to form electronic assemblies such as modules, circuit boards and stacked arrays.
REFERENCES:
patent: 5071792 (1991-12-01), VanVonno et al.
patent: 5138434 (1992-08-01), Wood et al.
patent: 5485039 (1996-01-01), Fujita et al.
patent: 5686317 (1997-11-01), Akram et al.
patent: 5851911 (1998-12-01), Farnworth
patent: 5888883 (1999-03-01), Sasaki et al.
patent: 5897337 (1999-04-01), Kata et al.
patent: 5904546 (1999-05-01), Wood et al.
patent: 6013948 (2000-01-01), Akram et al.
patent: 6060373 (2000-05-01), Saitoh
patent: 6080602 (2000-06-01), Tani et al.
patent: 6087845 (2000-07-01), Wood et al.
patent: 6107109 (2000-08-01), Akram et al.
patent: 6107164 (2000-08-01), Ohuchi
patent: 6114240 (2000-09-01), Akram et al.
patent: 6130111 (2000-10-01), Ikuina et al.
patent: 6136137 (2000-10-01), Farnworth et al.
patent: 6150717 (2000-11-01), Wood et al.
patent: 6153448 (2000-11-01), Takahashi et al.
patent: 6169329 (2001-01-01), Farnworth et al.
patent: 6177295 (2001-01-01), De Samber et al.
patent: 6180504 (2001-01-01), Farnworth et al.
patent: 6221751 (2001-04-01), Chen et al.
patent: 6233185 (2001-05-01), Beffa et al.
patent: 6281131 (2001-08-01), Gilton et al.
patent: 6294837 (2001-09-01), Akram et al.
patent: 6313531 (2001-11-01), Geusic et al.
patent: 6326698 (2001-12-01), Akram
patent: 6338980 (2002-01-01), Satoh
patent: 6350664 (2002-02-01), Haji et al.
patent: 6353267 (2002-03-01), Ohuchi et al.
patent: 6379999 (2002-04-01), Tanabe
patent: 6524890 (2003-02-01), Ueda et al.
patent: 6534387 (2003-03-01), Shinogi et al.
patent: 6579748 (2003-06-01), Okuno et al.
patent: 6607970 (2003-08-01), Wakabayashi
patent: 6649445 (2003-11-01), Qi et al.
patent: 10-79262 (1998-03-01), None
patent: 2000-31185 (2000-01-01), None
U.S. patent application Ser. No. 09/652,340, Farnworth.
U.S. patent application Ser. No. 09/640,801, Farnworth et al.
U.S. patent application Ser. No. 10/094,161, Farnworth et al., filed Mar. 6, 2002.
Advanced Coating Parylene Conformal Coating Specialists, advertising material, pp. 1-7, 1998.
Dexter Electronic Materials, Hysol FP4451 Material Properties, spec sheet, pp. 1-2, Aug. 20, 1999.
Dexter Electronic Materials, Hysol FP4450 Material Properties, spec sheet, pp. 1-2, Aug. 20, 1999.
Parylene Coating, advertising for Specialty Coating Systems, pp. 1-2, date unknown.
“Wafer Size CSP Packaging by VPES”, Japan Rec Co., advertising material, pp. 1-4, 1998.
David Francis & Linda Jardine, “Thin, Wafer-Level Package Is Made Without Damaging Die”, Chip Scale Review, May/Jun. 2002, p. 70.
Jeffrey C. Demmin, “More Wafer Thinning at ICAPS”, media new analysis, Mar. 13, 2002.
Doan Trung Tri
Wood Alan G.
Gratton Stephen A.
Graybill David E.
Micro)n Technology, Inc.
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