Semiconductor component having upper and lower mounting plates

Active solid-state devices (e.g. – transistors – solid-state diode – Lead frame – With structure for mounting semiconductor chip to lead frame

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Details

257692, H01L 23495

Patent

active

059820292

DESCRIPTION:

BRIEF SUMMARY
BACKGROUND OF THE INVENTION

The invention is directed to a semiconductor component with part with vertical MOS transistors, whereby secured on the mounting plate, semiconductor body and whereof at least one is electrically connected to the mounting plate.
Semiconductor components with such housings are known. Such housing forms are, for example, the DIL housing (Dual-In-Line) or P-DSO housing (Plastic-Dual-Small-Outline). The former housings are provided for normal mounting and the latter housings are provided for what is referred to as surface mounting (SMD) on printed circuit boards. These housings contain a metallic mounting plate as well as metallic leads that are electrically connected to the mounting plate or, respectively, the components secured on the mounting plate. The mounting plate and the leads are cut from a leadframe.
The semiconductor bodies are then connected to the leads via what is referred to as the bond wire technique.
It has turned out given semiconductor bodies that are composed of a logic part and of a power part with vertical MOS transistors that limits are placed on the realization of extremely low-impedance power switches due to the notoriously known bond wire technique. Given the employment, for example, of eight bond wires connected parallel having 50 .mu.m diameters, an additive on-state dc resistance of approximately 5 m.OMEGA. derives. Given a power switch with, for example, 25 m.OMEGA. overall on-state dc resistance, an added outlay of approximately 4 qmm silicon is caused in the semiconductor body for the compensation of the impedance caused by the parallel bond wires.
Moreover, multiple bondings are generally undesirable and represent a quality problem.


SUMMARY OF THE INVENTION

The invention is therefore based on the object of improving a semiconductor component of the species initially cited such that an added outlay of silicon is unnecessary and especially low-impedance power switches can be realized.
This object is inventively achieved with a semiconductor element that is characterized in that the housing comprises a number of upper mounting plates corresponding to the number of power parts, said number of upper mounting plates being electrically conductively secured on the upper sides of the power parts of the semiconductor body and being electrically connected to leads.
As a result of this concept, an extremely low-impedance main current path is achieved from the lower mounting plates and the lower leads to the upper mounting plate and the upper leads given power parts with vertical MOS transistors.
A further advantage is comprised therein that the upper mounting plate lies very close to the active semiconductor layer of the vertical MOS transistors. As a result thereof, the upper mounting plate forms a very good thermal storing capacity for the power switch. This is particularly advantageous in the employment of the semiconductor component given brief-duration dissipated power absorption.
In a preferred embodiment, the lower leads covered by the upper leads are recessed and the upper and lower leads lie in a common plane. As a result thereof, the semiconductor body is packed sandwich-like and no problems given introduction into the housing derive.
Typically, the housing is cuboid and the leads project from the housing at the long sides.


BRIEF DESCRIPTION OF THE DRAWINGS

The features of the present invention which are believed to be novel, are set forth with particularity in the appended claims. The invention, together with further objects and advantages, may best be understood by reference to the following description taken in conjunction with the accompanying drawings, in the several Figures of which like reference numerals identify like elements, and in which:
FIG. 1 a view onto the conductor system of the semiconductor component; and
FIG. 2 a section along the line I--I from FIG. 1.


DESCRIPTION OF THE PREFERRED EMBODIMENTS

The semiconductor component according to FIG. 1 is accommodated in a fully insulating housing 20 of plastic. The exterior contour of

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patent: 5448106 (1995-09-01), Fujitsu
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patent: 5763952 (1998-06-01), Lynch et al.
Electronic Design, vol. 42, No. 9, May 2, 1994, Frank Goodenough, P-DMOSFET and TSSOP Turns on with 1.7 V.sub.GS, pp. 89-95.
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IEEE International Solid State Circuits Conference, vol. 31, Sandro Storti et al, A 30A 30V DMOS Motor Controller and Driver, pp. 192/193.
Elektronik, vol. 38, No. 11, May 26, 1989, Helmuth Lemme, Kraft und Intelligenz Vereint, pp. 80-83.
Siemens Components, vol. 30, No. 6, Alfons Graf, Smart SIPMOS Power Switches in Standard SMD Packages: Silicon instead of heat sinks, pp. 31-34.
Electronic Engineering, Dec. (1991), Y. Kasem et al, High-Performance Power Package for Power IC Devices--Part 1, pp. 35-43.
Elektronik 24/1992, Gerhard Moosburger, Smarte Intelligenz, pp. 28-31.

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