Semiconductor component for vertical integration and manufacturi

Semiconductor device manufacturing: process – Making device or circuit responsive to nonelectrical signal – Responsive to electromagnetic radiation

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Details

438622, 438611, 438619, 438117, H01L 2100, H01L 214763

Patent

active

059305967

DESCRIPTION:

BRIEF SUMMARY
BACKGROUND OF THE INVENTION

The present invention is directed to a semi-conductor component for vertical integration with terminal contacts specifically fashioned for reversible contacting, and is also directed to an appertaining manufacturing method.
The vertical integration of semiconductor components, i.e. the arrangement of different function levels above one another, allows a parallel communication of these components with low outlay, electrically conductive connection in one level, and speed-limiting interchip connections are also avoided. Despite enhanced functionality, moreover, such a vertically integrated semiconductor chip can be accommodated in the same housing. A possibility of reversible contacting for these circuit levels with extremely miniaturized terminals must be available both for the manufacture of these components as well as for the required test of individual circuit levels integrated therein.
French reference FR-A-2 188 309 (corresponding to U.S. Pat. No. 3,825,353) discloses a semiconductor component on whose upper side a contact is secured to a flexible metal arm. This contact serves for mounting the component on a motherboard, whereby the contact is pressed against a contact surface of the motherboard, and the mechanical tension in the metal arm assures an adequately firm contacting of the contacts. European reference EP 0 238 089 A3 (corresponding to U.S. Pat. No. 4,939,568) discloses a three-dimensionally integrated circuit and an appertaining manufacturing method. A plurality of semiconductor levels with terminal contacts at the upper sides are arranged in a vertical stack and durably joined to one another by a thermoplastic resin.


SUMMARY OF THE INVENTION

An object of the present invention is to specify a semiconductor component that is suitable for reversible vertical integration, particularly for the purpose of testing further circuit levels. The method for manufacturing should a component should also be recited.
In general terms the present invention is a method for the manufacture of a semiconductor component, the method having the following steps: in a first step, a layer structure defined by an intended functioning of the semiconductor component is applied onto a substrate; in a second step, an insulating layer is applied that leaves a region provided for electrical connection free; in a third step, a terminal metallization is applied and structured; in a fourth step, dielectric is applied surface-wide; in a fifth step, a hole is produced in this dielectric, so that the terminal metallization is uncovered; in a sixth step, this hole is filled with a metal for forming a contact rod; in a seventh step, so much of the dielectric is removed that the contact rod projects beyond the upper side as intended, and in an eighth step, the contact rod and a portion of the terminal metallization adjacent thereto are uncovered by etching a surrounding opening.
Advantageous developments of the present invention are as follows.
The fourth step is implemented in that a first dielectric layer, an etch stop layer and a second dielectric layer are applied surface-wide. The fifth step is implemented in that a hole is etched into these dielectric layers and into this etch stop layer, so that the terminal metallization is uncovered. The seventh step is implemented in that the second dielectric layer is removed down to the etch stop layer.
In the above-described method, a semiconductor component is used for testing a further semiconductor component. The semiconductor components are provided with functional structures adapted to this test. The semiconductor components are brought into contact with one another such that the contact rod of the one semiconductor component is pressed against a contact of the other semiconductor component firmly enough for an electrically conductive connection.
Terminal contacts for vertical contacting are applied on an upper side in the inventive semiconductor component. These contacts are seated on a structured metal layer that is anchored in a layer structure

REFERENCES:
patent: 3760238 (1973-09-01), Hamer et al.
patent: 5521104 (1996-05-01), Walker
patent: 5612257 (1997-03-01), Tserng et al.
patent: 5763321 (1998-06-01), Ohshima et al.

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