Semiconductor component and corresponding test method

Details Semiconductor component and corresponding test method Semiconductor component and corresponding test method

2002-09-25

2004-07-13

Nelms, David (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Regenerative type switching device

Device protection

C257S327000, C257S339000, C257S355000, C257S356000, C257S367000

Reexamination Certificate

active

06762440

ABSTRACT:

TECHNICAL FIELD
The present invention relates to a semiconductor component having a first main terminal; a second main terminal; a control terminal for controlling the current flowing between the main terminals; and a first diode device, which can be connected between the first main terminal and the control terminal and has a first breakdown voltage such that it short-circuits the first main terminal to the control terminal and thus switches on the semiconductor component if the voltage dropped across the first diode device exceeds a predetermined value; the first diode device being connected to the control terminal in an integrated manner.
BACKGROUND ART
In this case, “short-circuiting” means that a current flow is made possible without a large additional resistance, while the voltage dropped across the first diode device is preserved.
Although applicable to any desired semiconductor components, the present invention and the problems on which it is based are explained with regard to vertical IGBT transistors or DMOS transistors.
In many applications of semiconductor power switches, the current is switched off in the case of an inductive load, for example for ignition transistors or ignition IGBTS. In this case, the current driven by the inductance, in avalanche breakdown, must be passed through the component if the component is not additionally protected. In this case, there is the risk of the component being irreversibly destroyed. One possibility for protection is active zener protection, as is known from J. Stengl, J. Tyihanyi, Leistung-MOS-FET-Praxis [Power MOS-FETs in practice], 2
nd
Edition, pages 130-133, Pflaum Verlag Munich, 1992.
It essentially comprises a zener diode or a zener diode chain between the gate and the drain of the transistor to be protected, which switches on the gate when the breakdown voltage of the zener diode is exceeded, and thus enables a current flow without a further rise in the drain-source voltage. In this way, the current can be passed uniformly via the entire cell array of the transistor or IGBT. As a result, in the event of switch-off, a very high energy can be taken up in the component without the component being destroyed.
In order that this effect of the active zener protection is actually achieved, it is essential that the voltage at which avalanche breakdown commences locally (e.g. in the edge region) or else globally in the cell array (avalanche voltage) is higher than the breakdown voltage of the zener diode (zener voltage).
Z. John Shen, Stephen P. Robb, Proceedings of 1998 ISPSD, Kyoto, pp. 97-100 (1998), propose an IGBT with active zener protection by a polydiode chain. The polydiode chain is arranged above a locally widened section of the edge termination and is connected on one side to the gate and on the other side to an n-doped region (e.g. the channel stopper of the edge termination) which is at the collector potential (rear-side potential) when reverse voltage is present. The edge termination itself comprises floating field rings which have simply been widened in the region of the polydiodes (with unchanged distance between the field rings). The breakdown characteristic curve of such an IGBT with integrated zener diode shows only the voltage at which the IGBT starts to carry current via the MOS channel opened by the active zener protection, but not where the avalanche voltage of the IGBT lies.
In order to be able to guarantee an adequate safety margin between zener voltage and avalanche voltage whilst taking account of manufacturing variations, it is necessary, therefore, to put the avalanche voltage far in excess of the zener voltage, for example about 200 V in accordance with this document. This in turn has the effect that the forward voltage or the on resistance of the IGBT or of the transistor is correspondingly increased.
It is not possible to directly check the safety margin at the wafer level. Therefore, the energy which can be taken up without destruction in the case of an inductive switch-off operation can only be tested on completely constructed systems. Such a test is referred to as UIS test (UIS=Unclamped Inductive Switching).
EP 0 845 813 A1 discloses an arrangement in which a bonding wire is used to produce a conductive connection between the lead frame or substrate at rear-side potential and a base contact in order to enable the IGBT to be switched off more rapidly. However, this document does not deal with active zener protection.
FIG. 5
shows a diagrammatic illustration of a known semiconductor component.
FIG. 5
shows the basic construction of an IGBT or power transistor (depending on whether the region 30 is n
+
- or p
+
-conducting) with an integrated active zener protection in silicon technology.
In
FIG. 5
,
40
designates a rear-side metalization layer as drain terminal or collector terminal,
30
designates a drain region (n
+
) or a collector region (p
+
),
20
designates a first base region of the n
−
conduction type,
50
designates a second base region of the p conduction type,
60
designates a source region or emitter region of the n
+
conduction type,
90
designates an insulator layer in the form of an oxide layer,
70
designates a gate,
100
designates a zener diode chain which, at one end, is connected to the gate
70
and, at the other end, is connected via a contact bridge
105
to an n-type well
110
within the first base region
20
.
The zener diode chain
100
is realized by a series circuit of a plurality of polysilicon zener diodes which are insulated from the active region of the semiconductor component by means of the oxide layer
90
.
In this connection, there are various possibilities for configuring the edge termination. A further example for the edge termination is constituted by floating field rings, as known from Z. John Shen et al. (aaO).
FIG. 6
shows a diagrammatic illustration of a further known semiconductor component.
In accordance with
FIG. 6
, two floating field rings of the p conduction type
52
,
54
are provided, which are connected via the connecting regions V
1
, V
2
to the zener diode chain divided into three parts
100
a, b, c.
FIG. 7
shows a diagrammatic illustration of yet another known semiconductor component.
In accordance with
FIG. 7
, field plates V
3
, V
4
are provided in order to connect the zener diode chain divided into three parts
100
a, b, c.
SUMMARY OF THE INVENTION
It is an object of the present invention to develop further the semiconductor component mentioned in the introduction in such a way that it can be tested better. A further object is to provide a corresponding test method.
According to the invention, this object is achieved by means of the semiconductor component specified in claim
1
and by means of the test method specified in claim
11
.
The idea underlying the present invention is that the first diode device has a first external contact-making region for connection to the first main terminal. In other words, the active zener protection is initially still not connected at the wafer level, so that the zener voltage and the avalanche voltage can be measured independently of one another. In the course of mounting in a housing, the zener protection is connected by means of a small additional outlay in the form of a bonding from the lead frame onto a contact-making region on the chip. Further appropriate measures can be taken to ensure that the avalanche voltage is not corrupted by the zener diode chain that is arranged in the edge region and not yet connected.
The essential advantage of the configuration according to the invention is that the zener voltage and the avalanche voltage can be measured separately from one another, so that it is possible to guarantee a safety margin of sufficient size between zener voltage and avalanche voltage, to be precise already at the wafer level. As a result, on the one hand it is possible to guarantee and test a safety margin between the zener voltage and the avalanche voltage, and on the other hand this safety margin can be dimensioned

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