Semiconductor clock signal generation circuit

Details Semiconductor clock signal generation circuit Semiconductor clock signal generation circuit

1995-12-12

1997-10-07

Callahan, Timothy P.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

327291, H03L 706

Patent

active

056752741

ABSTRACT:
A clock signal generating circuit is capable of testing a delay line loop (DLL) circuit by a method wherein, when an LSI circuit operates at a lower speed for a burn-in test, etc., the DLL circuit performs the same operation as when the LSI circuit operates normally at a high speed. This invention includes a selector for selecting either a reference clock signal or a test clock signal having a different phase with respect to the reference clock signal, and a delay line loop system phase-locked loop circuit for giving a delay to an output signal of the selector so as to get rid of a phase difference between the reference clock signal and an internal clock signal that has been propagated through a circuit to be supplied with a clock, and for generating the clock signal to be supplied to the circuit.

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