Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor
Reexamination Certificate
2000-05-08
2002-08-06
Everhart, Caridad (Department: 2825)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
C438S113000, C438S108000, C438S112000, C438S127000, C438S129000, C257S778000, C257S780000, C257S783000, C257S787000, C257S728000
Reexamination Certificate
active
06429043
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor circuitry device packaging a semiconductor chip and a method for manufacturing a same.
2. Description of the Related Art
In general, a semiconductor device is used in a state where it is encapsulated in a package in consideration of its use environments, packaging characteristics on a substrate or a like. Various types of packages are available depending upon sizes of semiconductor devices, a number of terminals or a like. For example, if the semiconductor device has many terminals, a BGA (Ball Grid Array) package in which terminals are mounted at a lower side face of the package in a lattice-like configuration or an LGA (Land Grid Array) package is employed in many cases.
One example of a process of encapsulating semiconductor chips in such kinds of packages will be described below by referring to
FIGS. 10A
to
10
G.
First, a lead frame
111
is provided (FIG.
10
A). The lead frame
111
is generally composed of low-cost Cu (copper) metal. Then, a recess
112
is formed in the lead frame
111
at a predetermined place by half-etching (FIG.
10
B). The recess
112
is formed at a place where an external terminal of a package is mounted. Then, plating is performed on an inside face of the recess
112
(FIG.
10
C). A plated layer
113
formed by this process serves as the external terminal
117
in a finished package. As described later, it is necessary for the external terminal to have various characteristics including its applicability to a wire bonding, its ability to prevent tin contained in a solder from being diffused, its wettability to soldering or a like. To meet such requirements, the plated layer
113
is constructed so as to be multi-layered, for example, in four layers composed of Pd/Ni/Pd/Au (Palladium/Nickel/Palladium/Gold). Then, a chip
101
is mounted with an insulating adhesive at a predetermined place on the half-etched side of the lead frame
111
(FIG.
10
D). In the example shown in
FIG. 10D
, the chip
101
is mounted face up. After a stud bump
115
required to ensure flatness is formed on the plated layer
113
, a connection between the stud bump
115
and the chip terminal
102
is established using a wire
114
(i.e., the wire bonding is carried out) (FIG.
10
E).
Then, the chip
101
, wire
114
or a like are formed in one piece of resin
116
for encapsulation. This causes the chip
101
or the like to be covered by resin
116
(FIG.
10
F). At a last stage, the lead frame
111
is totally removed by etching. At this point, however, the plated layer
113
is not removed by the etching. After the lead frame
111
is removed by the etching, the plated layer
113
serves as the external terminal
117
of the package (
FIG. 10G
) The external terminal
117
(the plated layer
113
) is firmly bonded to the stud bump
115
formed on a rear side of the stud bump
115
. The stud bump
115
itself is fixed by a resin mold, preventing the external terminal
117
from being peeled off.
Examples of such technologies of encapsulating semiconductor devices are disclosed in Japanese Laid-open Patent Application Nos. Hei9-162348 and Hei11-17054. Japanese Laid-open Patent Application No. Hei8-97399 is a technology in which a pillar-shaped conductor is mounted on a semiconductor chip.
However, such conventional technologies as disclosed in the above Japanese Laid-open Patent Application No. Hei9-162348 have a problem in that time required for manufacturing the semiconductor circuitry device is too lengthened, resulting in a decreased efficiency in its production. Time required for etching the lead frame, in particular, is a problem. Moreover, a formation of the stud bump is necessary in the conventional technologies, which causes the wire bonding to require much time. Though there is a remarkable tendency that a size of the package is being made smaller in this field recently, the conventional technologies are not successful in miniaturizing the package. The portion of the wire bonding in particular is an obstacle to the miniaturization of the package.
Moreover, the technology disclosed in Japanese Laid-open Patent Application No. Hei8-97399 requires that the pillar-like conductor is formed in the semiconductor chip, which is, however, difficult to be implemented technologically. Even if it were to be implemented, it is inevitable that a cost of a product would rise too much.
SUMMARY OF THE INVENTION
In view of the above, it is an object of the present invention to provide a compact semiconductor circuitry device capable of providing a high production efficiency and a method for manufacturing a same.
According to a first aspect of the present invention, there is provided a semiconductor circuitry device used by being connected to a connecting terminal section of other device including:
a semiconductor chip on a surface of which a circuit and an internal terminal are formed; and
an external terminal whose package connecting face to be connected to the connecting terminal section of the other device is mounted directly below the internal terminal.
By configuring as described above, it is possible to make the semiconductor circuitry device compact.
In the foregoing, a preferable mode is one that wherein further includes a bump mounted between the internal terminal and the external terminal used to connect the external terminal to the internal terminal.
By using the bump described above, the semiconductor circuitry device can be made smaller in size.
Also, a preferable mode is one that wherein further includes a resin portion formed, at least, on a surface of the bump and in an area surrounding the bump.
In some cases, a stress caused by connecting procedures remains in the bump and in an area surrounding the bump, which may cause breakage in a connection portion including the bump.
By mounting the resin portion described above, the stress can be relieved, thus preventing such breakage.
Also, a preferable mode is one wherein the package connecting face of the external terminal is disposed outside of the resin portion or the package connecting face conforms positionally to an outer face of the resin portion.
By configuring above, a connection with the connecting terminal of other device can be easily achieved. However, if high reliability in strength or a like is not required at a connecting point with the connecting terminal of other device, the package connecting face is allowed to confirm positionally to the outer face of the resin portion.
Also, a preferable mode is one that wherein a coated portion covers a side of the semiconductor chip on which the circuit is not mounted.
By configuring above, the semiconductor circuitry device can be resistant to various use environments.
Also, a preferable mode is one wherein the bump mounted between the internal terminal and the external terminal contains Au (Gold) or PbSn (Lead/Tin).
Also, a preferable mode is one that wherein includes a bump for packaging used to connect the package connecting face of the external terminal to the connecting terminal section of the other device.
Furthermore, a preferable mode is one wherein the bump for packaging is formed so as to be almost spherical.
According to a second aspect of the present invention, there is provided a method for manufacturing the semiconductor circuitry device having a semiconductor chip on a surface of which a circuit and an internal terminal are formed and having an external terminal connected to the internal terminal, including the steps of:
connecting a conducive material, which serves as the external terminal, fixed to a base material in a same pattern as for the internal terminal and in a state where the base material is able to be peeled off, to the internal terminal of the semiconductor chip while the conductive material is being attached on the base material; and
peeling the base material away from the conductive material after the conductive material is connected to the internal terminal of the semiconductor chip.
By employing the step of peeling the ba
Hirasawa Koki
Nakazawa Taibo
Everhart Caridad
Keshavan Belur
NEC Corporation
Young & Thompson
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