Semiconductor circuit including electrostatic discharge...

Electricity: electrical systems and devices – Safety and protection of systems and devices – Load shunting by fault responsive means

Reexamination Certificate

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C361S111000

Reexamination Certificate

active

08045304

ABSTRACT:
A semiconductor circuit includes, a first pad for a first power source, a second pad for a second power source, a third pad for an input/output signal, a protection element arranged between the third pad and the second pad; and a transistor functioning as a trigger element for use in flowing a trigger current to the protection element. The transistor includes a gate and a backgate being connected to the first pad and is connected to the protection element such that a source potential of the transistor becomes lower than a potential of the third pad, based on a voltage drop caused by the protection element, when potentials of the first pad and the third pad are kept at a power supply voltage level.

REFERENCES:
patent: 6545321 (2003-04-01), Morishita
patent: 7071528 (2006-07-01), Ker et al.
patent: 7256976 (2007-08-01), Sato
patent: 7405435 (2008-07-01), Sato
patent: 2003-203985 (2003-07-01), None
patent: 2003-318265 (2003-11-01), None
patent: 2006-303110 (2006-11-01), None
M. Mergens, et al. Speed Optimized Diode-Triggered SCR (DTSCR) for RF ESD Protection of Ultra-Sensitive IC Nodes in Advanced Technologies, IEEE rans. Device Materi. Reliab. vol. 5, No. 3, pp. 532-542, Sep. 2005.
Keppens, et al., “ESD Protection Solutions for High Voltage Technologies”, 2004 EOS/ESD Symposium.

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