Patent
1987-07-27
1991-10-08
James, Andrew J.
357 54, 357 67, H01L 2348, H01L 2934, H01L 2946
Patent
active
050559087
ABSTRACT:
The disclosure relates to a semiconductor circuit on a single chip, preferably of gallium arsenide, wherein insulating layers with vias therein for receiving metallization include a thin silicon nitride layer beneath a relatively much thicker silicon oxide layer with the nitride exposed on the via side walls to contact gold in the metallization within the via. The disclosure further includes metallization formed as a TiW/Au/TiW sandwich wherein the TiW layer contacting the insulator on the substrate is formed of a first tensile film of TiW with a compressive film of TiW of substantially the same thickness thereover and in contact therewith to lower the tensile force applied by the tensile layer, yet maintain the resultant force tensile.
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Delaney Joseph B.
Fuller Clyde R.
Skinner Robbie W.
Grossman Rene E.
James Andrew J.
Ngo Ngan V.
Sharp Melvin
Texas Instruments Incorporated
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