Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Having specific delay in producing output waveform
Reexamination Certificate
2002-09-30
2004-07-20
Ton, My-Trang Nu (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Having specific delay in producing output waveform
C327S276000
Reexamination Certificate
active
06765423
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor integrated circuit having receiver circuits that receive input signals in synchronization with a clock signal.
2. Description of the Related Art
In general, the semiconductor integrated circuit constituting a system operates in synchronization with a clock signal. This kind of system usually utilizes a single clock signal as the system clock for simplification of system design. The semiconductor integrated circuit in the system receives multiple-bit input signals in synchronization with the clock signal.
The timing of supplying the input signals to the semiconductor integrated circuit is defined by the setup and hold times relative to the clock signal. The setup time is a time required before a capturing edge of the clock signal, while the hold time is a time required after the capturing edge of the clock signal.
In semiconductor integrated circuits, the wire lengths are often made even so as to prevent a discrepancy from occurring between the timings of transmitting the multiple-bit data signals, address signals and so on (hereinafter referred to as “bus signals”). Also in the systems incorporating semiconductor integrated circuits, the wire lengths of the system bus lines are made even so as to prevent a discrepancy from occurring between the timings of the bus signals.
However, the timings of operations of the internal circuit of the semiconductor integrated circuit vary due to a change in temperature and a fluctuation in the supply voltage. Thus, even though the wire lengths of the signal lines have been made even, there may occur a discrepancy in timing between the bus signals transmitted within the semiconductor integrated circuit due to a change in temperature and a fluctuation in the supply voltage.
The setup and hold times of the input signals including the bus signals must be determined in view of the variation in the signal timings caused by a change in temperature and a fluctuation in the supply voltage as described above. Since this kind of timing variation is not dependent on the clock period, the higher the frequency of the clock signal is, relatively the larger the timing variation is. Accordingly, the higher the frequency of the clock signal is, relatively the longer the setup and hold times are. For this reason, in a system using the clock signal of high frequency, the frequency of the clock signal may be restricted by the setup and hold times. In other words, there may be a case that the transmission rate of the bus signals cannot be increased due to the restriction by the setup and hold times.
SUMMARY OF THE INVENTION
It is an object of the present invention to ensure that a semiconductor integrated circuit, which receives multiple-bit signals in synchronization with a clock signal, receives those signals without fail.
It is another object of the present invention to increase the transmission rate of the system constituted by the semiconductor integrated circuit.
According to one of the aspects of the semiconductor integrated circuit of the present invention, a first receiver circuit has a variable delay circuit, a decision circuit, and a delay adjustment circuit. The variable delay circuit delays a first input signal in accordance with a delay adjustment signal and outputs the delayed signal as a first delay signal. The decision circuit outputs, in accordance with a phase difference between the first delay signal and a clock signal, an increase signal to increase the delay time in the variable delay circuit or a decrease signal to decrease the delay time in the variable delay circuit. The delay adjustment circuit generates, in accordance with the increase or decrease signal, the delay adjustment signal to adjust the variable delay circuit.
For example, when the temperature of the semiconductor integrated circuit rises and the phase of the first input signal within the integrated circuit is delayed relative to the clock signal, the decision circuit outputs the decrease signal. The delay adjustment circuit generates the delay adjustment signal to shorten the delay time in the variable delay circuit. Thus, even when a discrepancy in timing between the first input signal and the clock signal occurs due to a change in temperature, a fluctuation in voltage or the like, the first receiver circuit can receive the first input signal without fail, in synchronization with the clock signal.
Since the timing of receiving the first input signal can be automatically adjusted within the first receiver circuit, the valid period (the setup and hold times) of the first input signal relative to the clock signal can be minimized. As a result, the frequency of the clock signal can be prevented from being restricted by the valid period, and the transmission rate of the first input signal can be increased.
In general, the input signals do not change in level as frequently as the clock signal. For this reason, the frequency of internal operations of the variable delay circuit that receives the first input signal is lower than the frequency of internal operations of the variable delay circuit that receives the clock signal. As a result, the power consumption in the variable delay circuit can be reduced.
According to another aspect of the semiconductor integrated circuit of the present invention, the decision circuit has a delay circuit, a level detecting circuit, and a delay-time control circuit. The delay circuit generates a standard delay signal obtained by delaying the first delay signal (or the first input signal) by a predetermined time, a previous delay signal whose phase is earlier than the phase of the standard delay signal, and a subsequent delay signal whose phase is later than the phase of the standard delay signal. The level detecting circuit detects, in synchronization with the clock signal (or the delay clock signal), an agreement or disagreement in logic level between the standard delay signal and the previous delay signal and an agreement or disagreement in logic level between the standard delay signal and the subsequent delay signal. When the first input signal deviates in timing from the clock signal, there occurs a disagreement in logic level between the standard delay signal and the previous or subsequent delay signal.
The delay-time control circuit outputs the increase signal when a logic level between the standard delay signal and the previous delay signal is in disagreement and outputs the decrease signal when a logic level between the standard delay signal and the subsequent delay signal is in disagreement. Then, the delay time of the first input signal is adjusted, and the first receiver circuit is prevented from receiving the first input signal of an incorrect level.
In this way, comparing the three signals of different timings (the previous, standard, and subsequent delay signals) in synchronization with the clock signal allows the timing deviation of the first input signal to be easily detected and the first input signal to resume the correct timing.
According to another aspect of the semiconductor integrated circuit of the present invention, the delay-time control circuit has an inhibiting circuit. The inhibiting circuit inhibits the increase and decrease signals from being outputted when both of the previous and subsequent delay signals disagree in logic level with the standard delay signal. If the valid period (timing specification) of the first input signal relative to the clock signal is short, there may occur a disagreement in level between the standard delay signal and the previous or subsequent delay signal even when the timing of the first input signal is correct. In such a case, the timing of the first input signal can be prevented from being erroneously adjusted.
According to another aspect of the semiconductor integrated circuit of the present invention, the decision circuit has a delay circuit, a level detecting circuit, and a delay-time control circuit. The delay circuit generates a standard delay signal obtained by delaying the first del
Arent Fox PLLC.
Fujitsu Limited
Nu Ton My-Trang
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