Semiconductor circuit device operating in synchronization with c

Details Semiconductor circuit device operating in synchronization with c Semiconductor circuit device operating in synchronization with c

1998-07-16

1999-12-07

Nelms, David

Static information storage and retrieval

Addressing

Sync/clocking

36523008, G11C 800

Patent

active

059994835

ABSTRACT:
A synchronous DRAM includes a mode register, and a logic circuit controlling the drivability of a CMOS output buffer circuit in response to a signal which is set in the mode register. The output buffer circuit includes a plurality of P channel MOS transistors and an N channel MOS transistor. A signal which corresponds to the frequency of an external clock signal is set in the mode register. The logic circuit selectively turns on/off the plurality of P channel MOS transistors. When the frequency is low, the number of transistors which are turned on is reduced, and the drivability of the buffer circuit is lowered. Accordingly, a ringing phenomenon is suppressed.

REFERENCES:
patent: 4736119 (1988-04-01), Chen et al.
patent: 5157354 (1992-10-01), Saiki et al.
patent: 5289413 (1994-02-01), Tsuchida et al.
patent: 5694074 (1997-12-01), Kitade et al.
patent: 5708603 (1998-01-01), Tanaka
patent: 5796313 (1998-08-01), Eitan

Affiliated with

Also associated with

Rating

Semiconductor circuit device operating in synchronization with c does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor circuit device operating in synchronization with c, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor circuit device operating in synchronization with c will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-831891