Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – With pn junction isolation
Reexamination Certificate
1997-05-01
2001-02-27
Saadat, Mahshid (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
With pn junction isolation
C257S372000, C257S373000, C257S544000, C257S547000, C257S901000
Reexamination Certificate
active
06194776
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor circuit devices and a method of fabricating the same and, more particularly, to those including semiconductor devices having a triple-well structure, for example, an active device such as a MOS transistor, a CMOS circuit, and a storage device such as a memory cell array. The present invention also relates to a pattern constructing technique for a mask device serving as an equipment for fabrication of such semiconductor circuit devices.
2. Description of the Background Art
Semiconductor integrated circuit devices, particularly memory devices and the like, are required to reduce the influences of noises from a semiconductor substrate (effect (
1
)). More specifically, variations in GND potential applied to the substrate varies the back bias potential of a well region of a MOS transistor, varying the threshold value of the transistor accordingly. Thus, such influences must be prevented. Furthermore, memory devices and the like are required to prevent memory cell data destruction resulting from the injection of a minority carrier current from the substrate into storage nodes of basic memory cells (effect (
2
)).
From the above described viewpoint, it is a common practice for memory devices and the like to employ a triple-well structure wherein an N-type well region produced in a P-type semiconductor substrate completely surrounds a P-type well region of a memory cell array block comprised of an NMOS transistor, thereby accomplishing the effects (
1
) and (
2
).
FIG. 22
is a cross-sectional view of a semiconductor device having a conventional triple-well structure as disclosed in Japanese Patent Application Laid-Open No. 3-30468 (1991), for example. As illustrated in
FIG. 22
, a P-type well region
2
P is completely surrounded by an N-type well region
1
P produced in a P-type semiconductor substrate
5
P. A P-type contact region
3
for supplying the potential level of the P-type well region
2
P is formed in a part of the P-type well region
2
P which lies between a part of an insulation film
14
P adjacent the inner periphery of a sidewall portion
1
PW of the N-type well region
1
P and a part of the insulation film
14
P adjacent a first source/drain region
18
P. A potential VBB is supplied from the exterior to the contact region
3
to fix the potential of the P-type well region
2
P at the potential VBB. A ground potential GND is supplied to a contact region
4
P to fix the potential of the P-type semiconductor substrate
5
P at the potential GND.
However, the use of the triple-well structure as shown in
FIG. 22
accomplishes the effects (
1
) and (
2
) of the above descried triple-well structure but involves the need to provide in the P-type well region
2
P the contact region
3
for supplying the potential to the P-type well region
2
P in the triple-well structure. This results in the increased chip area of the semiconductor circuit device by the amount of the area occupied by the contact region
3
in the conventional triple-well structure as represented in FIG.
22
.
Additionally, in the conventional triple-well structure as shown in
FIG. 22
, the contact region
3
must be positioned at a peripheral position offset from the center toward the sidewall portion
1
PW in the P-type well region
2
P for structural reasons. Then, uniform supply of the potential throughout the P-type well region
2
P is not insured.
More high-capacity DRAMs have been constructed such that a memory cell array is divided into sub-arrays for low power consumption and high speed operation. In such a case, a divided word line structure comprised of main word lines and sub-word lines is sometimes employed as an example of word line structures to increase the operating speed of word drivers. In a semiconductor integrated circuit device having such a divided word line structure, if sub-decode circuits for the sub-word lines are comprised of CMOS circuits and located around a memory cell array sub-block, the memory cell array sub-block is surrounded by N-type well regions for PMOS transistors since sense amplifier circuit bands and sub-decode circuit bands positioned to surround the memory cell array sub-block are comprised of CMOS circuits. Such a construction makes it extremely difficult to position the contact region for supplying the potential of the P-type well region of the memory cell array sub-block within the memory cell array sub-block. As a result, the conventional triple-well structure fails to be applied to the semiconductor integrated circuit device having the divided word line structure.
Japanese Patent Application Laid-Open No. 2-196460 (1990) proposes a conventional triple-well structure similar to that illustrated in
FIG. 22
for decreasing the area occupied by a chip to reduce the size of a CMOS transistor. This technique, however, is not effective to solve the above described problems approached by the present invention since a P-type contact layer for supplying a fixed potential VSS is formed in an upper corner portion of a P-type well region immediately under each region of the transistor as illustrated in
FIG. 1
of the above described reference. Additionally, this technique employs the conventional N-type well region with one sidewall portion thereof completely removed in place of the N-type well region completely surrounding the P-type well region. Then, one side surface of the P-type well region is entirely connected to a P-type substrate. This structure increases the minority carrier current injected from the substrate, creating the new problem of losing the great majority of the original functions and effects of the triple-well structure.
Therefore, the technique disclosed in Japanese Patent Application Laid-Open No. 2-196460 (1990) is not practicable.
SUMMARY OF THE INVENTION
According to a first aspect of the present invention, a semiconductor circuit device comprises: a semiconductor substrate of a first conductivity type; a first well region of the first conductivity type extending from a first region of a surface of the semiconductor substrate into the semiconductor substrate; a second well region of a second conductivity type extending from a second region of the surface of the semiconductor substrate adjacent the first region into the semiconductor substrate so as to surround the first well region; at least one transistor comprising first and second transistor regions of the second conductivity type extending from the first region of the surface of the semiconductor substrate into the first well region, and a third transistor region formed on the first region of the surface between the first and second transistor regions; and at least one conduction region formed partially in a bottom portion of the second well region for providing electrical continuity between the first well region and the semiconductor substrate, wherein a contact region for supplying a predetermined potential to the first well region is not formed in the first well region.
The second well region almost completely surrounds the first well region to block almost all of the minority carriers from being injected from the semiconductor substrate into the first well region. In general, the space on the surface of the first well region is occupied by the transistor and the insulation layer for bounding the active area. Then, there is no space for the contact region on the surface.
In this state, the contact region is not formed in the first region of the surface, but only the conduction portion formed in the bottom portion establishes electrical connection between the first well region and the semiconductor substrate. In other words, the conduction portion functions as the sole fixed potential supply path for the first well region.
Preferably, according to a second aspect of the present invention, in the semiconductor circuit device of the first aspect, the at least one conduction region is of the first conductivity type.
The conduction region which is of the same conductivity type as the semicon
Amano Teruhiko
Tsukude Masaki
Eckert II George C.
Mitsubishi Denki & Kabushiki Kaisha
Oblon & Spivak, McClelland, Maier & Neustadt P.C.
Saadat Mahshid
LandOfFree
Semiconductor circuit device having triple-well structure in... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor circuit device having triple-well structure in..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor circuit device having triple-well structure in... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2606897