Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Including high voltage or high power devices isolated from...
Reexamination Certificate
1999-05-10
2001-09-18
Chaudhuri, Olik (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Including high voltage or high power devices isolated from...
C365S226000, C365S227000
Reexamination Certificate
active
06291869
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor circuit devices and, more specifically to a semiconductor circuit device having a hierarchical power supply structure.
2. Description of the Background Art
In a recent semiconductor memory, a threshold value of a transistor is becoming lower with decrease in an operating power supply voltage. To prevent an increase in subthreshold leakage current which is caused by the decrease in the threshold value of the transistor, various SCRC (Subthreshold Current Reduced Control) techniques are developed (see for example Japanese Patent Laying-Open No. 6-237164).
An internal control of a DRAM (Dynamic Random Access Memory) is divided into two types of operations, that is, row and column related operations. With recent tendency toward multiply banks and an independent operation for every bank, a structure of a circuit for controlling a bank is becoming more complicated. In addition, the number of circuits in a whole chip increases, thereby resulting in an increase in leakage current during stand-by.
According to the above described SCRC technique, a hierarchical power supply structure has been proposed to reduce subthreshold leakage current during such stand-by. In the hierarchical power supply structure, sub power supply and ground lines are provided in addition to main power supply and ground lines, a logic circuit such as a CMOS (Complementary Metal Oxide Semiconductor) inverter circuit outputting a signal at an H (logic high) level during stand-by is connected between the main and sub power supply lines, and a logic circuit such as a CMOS inverter circuit outputting a signal at an L (logic low) level is connected between the sub power supply line and the main ground line, so that the sub power supply and ground lines are electrically disconnected from the main power supply and ground lines during stand-by, respectively.
In such hierarchical power supply structure, a source of a P channel MOS transistor in the CMOS inverter circuit outputting the signal at the H level is connected to the main power supply line, whereas a source of an N channel MOS transistor is connected to the sub ground line. Thus, a source potential of the N channel MOS transistor is higher than a ground potential during stand-by, so that subthreshold leakage current for the N channel MOS transistor is reduced. On the other hand, a source of an N channel MOS transistor in the CMOS inverter circuit outputting the signal at the L level is connected to the main ground line, whereas a source of a P channel MOS transistor is connected to the sub power supply line. Thus, a source potential of the P channel MOS transistor is lower than a power supply potential during stand-by, so that subthreshold leakage current for the P channel MOS transistor is reduced.
Although the above described hierarchical power supply structure can be employed for a logic circuit in which a logic level of an output signal during stand-by is determined, it cannot be employed for that in which the logic level is not determined. Thus, such logic circuit has to be connected between the main power supply and ground lines, whereby subthreshold leakage current cannot be reduced during stand-by.
In a latch circuit, particularly, reduction in subthreshold leakage current cannot be achieved by the above described hierarchical power supply structure as a logic level of a signal to be latched is not determined during stand-by.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a semiconductor circuit device capable of reducing subthreshold leakage current even in a logic circuit in which a logic level of an output signal is not determined during stand-by.
Another object of the present invention is to provide a semiconductor circuit device capable of reducing subthreshold leakage current in a latch circuit.
According to one aspect of the present invention, a semiconductor circuit device having an operation mode and a stand-by mode includes main and sub power supply lines, a first switching element, main and sub ground lines, a second switching element, first buffer power supply and ground lines, second buffer power supply and ground lines, a plurality of first logic circuits, a plurality of second logic circuits and a selection circuit. The main power supply line receives a power supply voltage. The first switching element is connected between the main and sub power supply lines, and turned on and off in the operation and stand-by modes, respectively. The main ground line receives a ground voltage. The second switching element is connected between the main and sub ground lines, and turned on and off in the operation and stand-by modes, respectively. Each of the first logic circuits is connected between the first buffer power supply and ground lines for supplying an output signal at a first logic level in the stand-by mode. Each of the second logic circuits is connected between the second buffer power supply and ground lines for supplying an output signal at a second logic level which is complementary to the first logic level in the stand-by mode. The selection circuit connects the first buffer power supply and ground lines and second buffer power supply and ground lines to the main power supply line, sub ground line, sub power supply line and the main ground line, respectively, when the plurality of first logic circuits supply signals at a logic high level as the first logic level and the plurality of second logic circuits supply output signals at a logic low level as the second logic level in the stand-by mode. The selection circuit also connects the first buffer power supply and ground lines and the second buffer power supply and ground lines to the sub power supply line, main ground line, main power supply line and sub ground line, respectively, when the plurality of first logic circuits supply output signals at a logic low level as the first logic level and the plurality of second logic circuits supply output signals at a logic high level as the second logic level in the stand-by mode.
In the above described semiconductor circuit device, the logic circuit is selectively connected between the main power supply line and sub ground line or between the sub power supply line and main ground line in accordance with a logic level of the output signal to be supplied from the logic circuit. Thus, reduction in subthreshold leakage current is achieved by the hierarchical power supply structure even in the case of a logic circuit in which the logic level of the output signal in the stand-by mode is not determined.
According to another aspect of the present invention, a semiconductor circuit device having operation and stand-by modes includes main and sub power supply lines, a first switching element, main and sub ground lines, a second switching element, a plurality of first logic circuits, a plurality of second logic circuits and a voltage supplying circuit. The main power supply line receives a power supply voltage. The first switching element is connected between the main and sub power supply lines, and turned on and off in the operation and stand-by modes, respectively. The main ground line receives a ground voltage. The second switching element is connected between the main and sub ground lines, and turned on and off in the operation and stand-by modes, respectively. Each of the first logic circuits is connected between the main power supply line and the sub ground line for supplying an output signal at a first logic level in the stand-by mode. Each of the second logic circuits is connected between the sub power supply line and the main ground line for supplying an output signal at a second logic level which is complementary to the first logic level in the stand-by mode. The voltage supplying circuit supplies a voltage which is lower than the ground voltage for the sub ground line when the plurality of first logic circuits supply output signals at a logic low level as the first logic level and the plurality of second logic circuits supply
Chaudhuri Olik
Ha Nathan W.
McDermott & Will & Emery
Mitsubishi Denki & Kabushiki Kaisha
LandOfFree
Semiconductor circuit device having hierarchical power... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor circuit device having hierarchical power..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor circuit device having hierarchical power... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2542603