Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Having specific delay in producing output waveform
Reexamination Certificate
2000-11-22
2002-09-24
Callahan, Timothy P. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Having specific delay in producing output waveform
C327S285000, C327S272000
Reexamination Certificate
active
06456137
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor circuit including multiple wires in which cross-talk occurs, a delay adjustment method therefor and a layout method therefor, and more particularly to a semiconductor Circuit aiming at suppressing a variation of delay time, a delay adjustment method therefor and a layout method therefor.
2. Description of the Related Art
The semiconductor circuit contains multiple signal lines disposed in parallel to each other and, for example, a device such as inverter and buffer are provided to them at a matching position in a signal propagation direction.
FIG. 1
is a circuit diagram showing a structure of a conventional semiconductor circuit.
For example, two signal lines S
11
, S
12
are disposed in parallel to each other. Buffers BU
11
and BU
13
are disposed on the signal line S
11
in a signal propagation direction in this order. Then, buffers BU
15
and BU
14
are disposed on the signal line S
12
in the signal propagation direction in this order. The buffers BU
11
and BU
15
are disposed at a position matching with each other in the signal propagation direction, namely, adjacent position. The buffers BU
13
and BU
14
are disposed at a position matching with each other in the signal propagation direction. Therefore, the length of wire between the buffers BU
11
and BU
13
is equal to the length of wire between the buffers BU
15
and BU
14
.
A resistor having a resistance “R” parasitizes to each wire between the buffers BU
11
and BU
13
, and between the buffers BU
15
and BU
14
. Further, a capacitor having capacitance “C” parasitizes between wire between the buffers BU
11
and BU
13
, and the wire between the buffers BU
15
and BU
14
.
If a signal is inputted to the buffers BU
11
and BU
15
in the conventional semiconductor circuit having such a structure, the respective signals are driven by the buffers BU
11
and BU
15
and then inputted to the buffers BU
13
and BU
14
. At this time, a delay occurs in signal propagation. If changing signals are inputted to both the signal lines S
11
and S
12
, as compared to a case where a signal inputted to one signal line is not changed, the delay time is decreased by cross-talk if that input signal is in phase. If the input signal is in opposite phase, the delay is increased by the cross-talk.
An above-described variation of the delay time becomes more evident as the capacitance between the wires is increased. Therefore, there is provided a semiconductor circuit in which the capacitance between the wires is reduced by providing another buffer between the buffers.
FIG. 2
is a circuit diagram showing a structure of a conventional semiconductor circuit intended to reduce the capacitance between the wires.
In the conventional semiconductor circuit intended to reduce capacitance between the wires, a buffer BU
12
is connected between the buffers BU
11
and BU
13
and a buffer BU
16
is connected between the buffers BU
15
and BU
14
.
Next, an operation of the conventional semiconductor circuit having the above-described structure will be described.
FIGS. 3A-3D
are diagrams showing an operation of the conventional semiconductor circuit shown in FIG.
2
.
FIG. 3A
is a circuit diagram showing an operation when input signals rise on both the signal lines S
11
and S
12
.
FIG. 3B
is a circuit diagram showing an operation when a input signal rises on the signal line S
11
while a signal falls on the signal S
12
.
FIG. 3C
is a circuit diagram showing an operation when the input signal falls on the signal line S
11
while the signal rises on the signal line S
12
.
FIG. 3D
is a circuit diagram showing an operation when the input signals fall on both the signal lines S
11
, S
12
.
If both the signals propagated through the signal lines S
11
and S
12
rise, the signals propagated through the signal lines S
11
and S
12
are outputted from the buffers B
11
and BU
15
in non-inverted state as shown in FIG.
3
A. Because these output signals are in phase with each other, a delay time until they are inputted to the buffers BU
12
and BU
16
is decreased by cross-talk as compared to a case where the mating signal is not changed.
After that both the signals are outputted from the buffers BU
12
and BU
16
in non-inverted state. Because these output signals are in phase, the delay time until they are inputted to the buffers BU
13
and BU
14
is further decreased by the cross-talk as compared to a case where the mating signal is not changed.
On the other hand, if a signal propagated through the signal line S
11
rises while a signal propagated through the signal line S
12
falls, signals propagated through the signal lines S
11
and S
12
are outputted from the buffers BU
11
and BU
15
in non-inverted state. Because these signals are in opposite phase, the delay time until they are inputted to the buffers BU
12
and BU
16
is increased by cross-talk as compared to a case where the mating signal is not changed.
After that, both the signals are outputted from the buffers BU
12
and BU
16
in non-inverted state. Because these output signals are in opposite phase, the delay time until they are inputted to the buffers BU
13
and BU
14
is further increased by the cross-talk as compared to a case where the mating signal is not changed.
If a signal propagated through the signal line S
11
falls while a signal propagated through the Signal line S
12
rises, the signals are changed in opposite phase to
FIG. 3B
as shown in FIG.
3
C. If both signals propagated through the signal lines S
11
and S
12
fall, the signals are changed in opposite phase to
FIG. 3A
as shown in FIG.
3
D.
By providing with the buffers BU
12
, BU
16
in the conventional semiconductor circuit shown in
FIG. 2
, the driving performance is raised and the capacitance between wires is reduced so as to suppress a variation due to cross-talk.
To remove a timing shift generated by cross-talk between signals propagated through the adjacent two signal lines, such a semiconductor circuit having inverters to accelerate or retard propagation of signals has been proposed (Japanese Patent Application Laid-Open No. 8-330934).
However, in the conventional semiconductor circuit shown in
FIG. 2
, the delay time of a signal in phase is only decreased while the delay of a signal in opposite phase is only decreased because the buffers BU
12
and BU
16
added to the circuit shown in
FIG. 1
are of positive logic. Thus, it is necessary to provide with a multiplicity of buffers to suppress the variation of the delay time. As a result, there exists a problem that production cost is increased or the delay is increased due to a switching delay of a buffer.
Although in the conventional semiconductor circuit proposed in Japanese Patent Application Laid-Open No. 8-330934, a generated timing shift can be reduced, there is such a problem that if a signal having no timing shift is inputted, the signal propagation is forced to be accelerated or retarded.
SUMMARY OF THE INVENTION
The object of the present invention is to provide a semiconductor circuit capable of preventing a variation of the delay time caused by cross-talk, a delay adjustment method therefor and a layout method therefor.
According to one aspect of the present invention, a semiconductor circuit comprises first and second wires disposed adjacent to each other, and even pairs of buffers and inverters. A buffer and an inverter in each of the pairs are disposed on the first or second wires respectively. The first and second wires are respectively divided to even wire sections by the even pairs and a device or terminal connected to the output side of the pairs. Lengths of the wire sections are equal to each other between adjacent wire sections of the first and second wires. Gaps between the first and second wires are equal to each other between each two wire sections from the input side of the first and second wires.
According to another aspect of the present invention, a semiconductor circuit comprises first and second wires disposed adjacent to
Callahan Timothy P.
Foley & Lardner
NEC Corporation
Nguyen Hai L.
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