Fishing – trapping – and vermin destroying
Patent
1988-11-02
1989-10-17
Hearn, Brian E.
Fishing, trapping, and vermin destroying
437 31, 437200, 437245, 437 41, 437 45, 148DIG9, 148DIG10, 357 43, H01L 21265
Patent
active
048747173
ABSTRACT:
Integrated semiconductor circuits with at least one bipolar transistor (17) and at least one MOS field effect transistor (18) on a chip wherein contacts from a metal interconnect level to diffused active emitter (8) and collector (5) regions of the bipolar transistor (17) as well as the gate electrode (9) of the MOS transistor are composed of a high melting point silicide, such as tantalum, tungsten, molybenum or titanium silicide, are disclosed, along with a method of producing such circuits. In addtion to achieving independence from a metallization grid and achieving low-resistance wiring, the use of the silicide, in conjunction with the high temperature stability of silicides, enables its simultaneous use as an implantation mask. The invention allows the production of bipolar/MOS components on a chip without added outlay.
REFERENCES:
patent: 4180596 (1979-12-01), Crowder et al.
patent: 4283439 (1981-08-01), Higashinakagawa et al.
patent: 4299024 (1981-11-01), Piotrowski
patent: 4424578 (1984-01-01), Miyamoto
patent: 4436582 (1984-03-01), Saxena
patent: 4471376 (1984-09-01), Morcom et al.
patent: 4737472 (1988-04-01), Schaber
patent: 4752589 (1988-06-01), Schaber
patent: 4772567 (1988-09-01), Hirag
patent: 4778774 (1988-10-01), Blossfeld
patent: 4784971 (1988-11-01), Chin
patent: 4816423 (1989-03-01), Havemann
Electronics, Jun. 8, 1978, "How The Bi-Fet Process Benefits Linear Circuits", by Rod Russell et al, pp. 113-117.
IEEE Transactions on Electron Devices, vol. Ed-27, No. 8, Aug., 1980, "Application of MoSi.sub.2 To The Double-Level Interconnections of I.sup.2 l Circuits", by Sasaki et al, pp. 1385-1389.
IEEE Trans. on Elec. Devices, vol. ED-27, No. 8, Aug. 1980, "Subnanosecond Self-Aligned I.sup.2 L/MTL Circuits", by Tang et al, pp. 1379-1384.
Japan application No. 53-119537, Apr. 1, 1980, "Method of Manufacturing Semiconductor Device", Kenji Shibata.
IEEE Journal of Solid-State Circuits, vol. SC-15, No. 4, Aug., 1980, "Refractory Silicides of Titanium and Tantalum for Low-Resistivity Gates and Interconnects", by Murarka et al, pp. 474-482.
Neppl Franz
Schwabe Ulrich
Hearn Brian E.
McAndrews Kevin
Siemens Aktiengesellschaft
LandOfFree
Semiconductor circuit containing integrated bipolar and MOS tran does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor circuit containing integrated bipolar and MOS tran, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor circuit containing integrated bipolar and MOS tran will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1743430