Semiconductor circuit and semiconductor device

Details Semiconductor circuit and semiconductor device Semiconductor circuit and semiconductor device

2002-04-16

2003-11-11

Nguyen, Viet Q. (Department: 2816)

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

C365S226000, C365S227000, C365S201000

Reexamination Certificate

active

06646952

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a semiconductor circuit and a semiconductor device which optimize the driving power and power consumption and which are used for a SiP (System in a Package).
BACKGROUND OF THE INVENTION
FIG. 11
is a partial cross-sectional diagram that shows a structure of a conventional SiP. As shown in
FIG. 11
, a chip having a logic circuit formed thereon (“logic chip”)
2000
is provided on a die pad
3000
with a SiP
1100
. A chip having a memory like a DRAM formed thereon (“memory chip”)
1000
is mounted on this logic chip
2000
.
Each of the memory chip
1000
and the logic chip
2000
is provided with a pad (not shown) that is connected to an input/output circuit formed on each chip. In order to electrically connect between the memory chip
1000
and the logic chip
2000
, the pads provided on both chips are connected to each other via a wire
5000
b
. In order to electrically connect between the SiP
1110
and the outside (not shown), the pad provided on the logic chip
2000
is connected with an inner lead
7000
via a wire
5000
a
. In other words, input/output signals of the memory chip
1000
are input to/output from the wire
5000
a
via the logic chip
2000
, without being directly input to/output from a package.
When testing the memory chip
1000
and the logic chip
2000
in a wafer status respectively, the input/output signals of the memory chip
1000
and the logic chip
2000
are input to/output from the tested device directly from the respective pads. Therefore, the load becomes large, and it becomes necessary to secure the input/output driving power to bear the test.
When only the memory chip
1000
and the logic chip
2000
are packaged into one like the SiP
1100
, surplus driving power which-drives a chip outside exists in each input/output circuit of each chip.
However, during the normal use of the SiP
1100
, the load of the wire
5000
b
between the chips is small. Therefore, only the driving power is required to exist that can drive the load from the memory chip
1000
to the logic chip
2000
, or from the logic chip
2000
to the memory chip
1000
.
In the above conventional SiP
1100
, a chip having an input/output circuit that does not need to drive the package outside is not required to have the driving power which drives the load of the package outside. On the other hand, when this driving power is held, power consumption becomes larger.
When the driving power that is necessary for the testing is secured, this has a problem that the power consumption becomes larger than the driving power that is necessary for the normal use.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a semiconductor circuit capable of optimizing the driving power and power consumption, by changing the driving power of an input/output circuit at a test time and a normal use time.
The semiconductor circuit according to one aspect of the present invention comprises,
The semiconductor circuit comprising a buffer circuit and an input/output circuit. The buffer circuit has a first controller that is input with a first signal that becomes enable at the time of outputting data and becomes disable at the time of inputting data, and a second signal that is changed over in a test mode, and that outputs a third signal, and a second controller that is input with the first signal and an inverted signal of the second signal, and that outputs a fourth signal. The input/output circuit has a first driver that is input with the third signal, a second driver that is input with the fourth signal, and a third driver of which input terminal is connected to output terminals of said first driver and said second driver, and of which output terminal is connected to input terminals of said first driver and said second driver.
The semiconductor circuit according to another aspect of the present invention comprises a buffer circuit and an input/output circuit. The buffer circuit has a first controller that is input with a first signal that becomes enable at the time of outputting data and becomes disable at the time of inputting data, and a second signal that is changed over in a test mode, and that outputs a third signal, and a second controller that is input with the first signal, and that outputs a fourth signal. The input/output circuit has a first driver that is input with the third signal, a second driver that is input with the fourth signal, and a third driver of which input terminal is connected to output terminals of said first driver and said second driver, and of which output terminal is connected to input terminals of said first driver and said second driver.
The semiconductor device according to still another aspect of the present invention comprises the semiconductor circuit according to the present invention.
Other objects and features of this invention will become apparent from the following description with reference to the accompanying drawings.


REFERENCES:
patent: 5689465 (1997-11-01), Sukegawa et al.
patent: 6429729 (2002-08-01), Kobayashi et al.
patent: 2001/0050590 (2001-12-01), Kobayashi et al.
patent: 05-304212 (1993-11-01), None
patent: 08-220196 (1996-08-01), None

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