Semiconductor circuit alternately operative as a data latch and

Details Semiconductor circuit alternately operative as a data latch and Semiconductor circuit alternately operative as a data latch and

1982-11-15

1985-07-09

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307455, 307272A, H03K 3023, H03K 3037, H03K 3295, H03K 19086

Patent

active

045284652

ABSTRACT:
A high speed latch for integrated circuit applications employs a linear differential logic type gate and a cross coupled differential pair storage element which share common load terminals. The cross coupled differential pair is transparent to the operation of the gate circuit in one condition and operative to store the current state of the gate circuit in another condition. The linear differential pair is constrained to draw less current than the gate when there is contention between previously latched data and input data. Thus, the linear differential pair does not inhibit operation of the gate when the gate is enabled. To provide the desired effect the gate uses a current source and the differential pair employs a resistor.

REFERENCES:
patent: 3394267 (1964-12-01), Schmidt
patent: 3514640 (1970-05-01), Fett
patent: 3529184 (1970-09-01), Conklin
patent: 3663837 (1972-05-01), Epstein et al.
patent: 3796896 (1974-03-01), Fulton et al.
patent: 3800168 (1974-03-01), Cochran
patent: 4219744 (1980-08-01), Shinn
patent: 4276485 (1981-06-01), Rydval
patent: 4301379 (1981-11-01), Reinert

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